;-------------------------------------------------------------------------- ; ; ; PEEDI target configuration file for PXA270 processor ; ; Ronetix ; ; Supported devices : PXA270 ; ; Board : CM-X270L, NAND FLASH data bus is shifted with 16-bits ; NAND's DATA_BUS[7..0] is connected to CPU's DATA_BUS[23..16] ; ; Revision : 1.0 ; ; Date : Dec 19, 2006 ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. These licenses must be filled before using this file. ; The [LICENSE] section may contain license keys for one or more PEEDIs. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2010, 1111-1111-1111-1 ; KEY = XXXXX, 2222-2222-2222-2 ; ; The [LICENSE] section may point to an external file which contains ; license keys for one or more PEEDIs. The external file must include ; the text [LICENSE] followed by all keys. ; ; Example: ; [LICENSE] ; FILE = tftp://192.168.3.1/license.txt ; or ; FILE=eep:license.txt ; or ; FILE = ftp://user:password@192.168.3.1/license.txt ; ; ; PEEDI is shipped with license keys stored in "eep:license.txt" and ; printed on a label on the bottom side of PEEDI. ; [LICENSE] FILE=eep:license.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote ; gdb remote REMOTE_PORT = 2000 ; TCP/IP port [TARGET] PLATFORM = XScale ; platform is XScale [PLATFORM_XSCALE] JTAG_CHAIN = 7 ; list of IR length of all TAP controller in JTAG chain JTAG_CLOCK = 1000, 25000 ; JTAG Clock in [kHz] - 1MHz JTAG clock for init ; operations and 16MHz for normal work TRST_TYPE = PUSHPULL ; type of TRST output: OPENDRAIN or PUSHPULL RESET_TIME = 20 ; length of RESET pulse in ms; 0 means no RESET WAKEUP_TIME = 20 TIME_AFTER_RESET = 2500 CORE0 = XScale, 0 ; TAP is XSCALE CPU CORE0_STARTUP_MODE = RESET ; Stop core CORE0_BREAKMODE = soft ; breakpoint mode: CORE0_INIT = INIT_CPU ; init section for board CORE0_FLASH0 = FLASH_NOR ; NOR flash section parameters CORE0_FLASH1 = FLASH_NAND ; NAND Flash section CORE0_ENDIAN = LITTLE ; core is little endian CORE0_WORKSPACE_ADDR = 0xA0001000 ; start address of workspace for ; flash programmer CORE0_WORKSPACE_LEN = 0x10000 ; length of workspace in bytes CORE0_DEBUG_HANDLER_ADDR= 0xFE000000 ; debug handler base address CORE0_VECTOR_CATCH_MASK = 0x00 ; catch data abort exceptions CORE0_VECTOR_UNDEF = AUTO CORE0_VECTOR_SWI = AUTO CORE0_VECTOR_PABORT = AUTO CORE0_VECTOR_DABORT = AUTO CORE0_VECTOR_RES = AUTO CORE0_VECTOR_IRQ = AUTO CORE0_VECTOR_FIQ = AUTO CORE0_RELOCATED_UNDEF = AUTO CORE0_RELOCATED_SWI = AUTO CORE0_RELOCATED_PABORT = AUTO CORE0_RELOCATED_DABORT = AUTO CORE0_RELOCATED_RES = AUTO CORE0_RELOCATED_IRQ = AUTO CORE0_RELOCATED_FIQ = AUTO CORE0_FILE = "myfile.bin", BIN, 0x00400000 ; default file CORE0_PATH = "tftp://192.168.3.1" ; default path [INIT_CPU] ; ; setup memory controller ; memory write 0x48000064 0x0000003C ; SA-1110 compatibility mode memory write 0x48000008 0x7FF47FF8 ; MSC0 memory read 0x48000008 memory write 0x4800000C 0x7FF41364 ; MSC1 memory read 0x4800000C memory write 0x48000010 0x133023F4 ; MSC2 memory read 0x48000010 memory write 0x48000014 0x00000000 ; MECR memory write 0x48000028 0x00040420 ; MCMEM0 memory write 0x4800002C 0x00000000 ; MCMEM1 memory write 0x48000030 0x00040420 ; MCATT0 memory write 0x48000034 0x00000000 ; MCATT1 memory write 0x48000038 0x00040420 ; MCIO0 memory write 0x4800003C 0x00000000 ; MCIO1 memory write 0x48000020 0x00000000 ; FLYCNFG ; ; setup SDRAM ; see page 71 dev kit memory write 0x48000004 0x23ca4015 ; MDREFR memory write 0x48000004 0x20ca2015 ; MDREFR memory write 0x4800001C 0x40044004 ; SXCNFG memory write 0x48000004 0x204b2015 ; MDREFR memory read 0x48000004 memory write 0x48000004 0x200b2015 ; MDREFR memory read 0x48000004 memory write 0x48000004 0x200bc015 ; MDREFR memory read 0x48000004 memory write 0x48000000 0x00001AC8 ; MDCNFG memory read 0x48000000 memory write 0x48000000 0x00001AC9 ; MDCNFG memory read 0x48000000 wait 20 ; ; step 7 - Trigger 8 SDRAM refresh cycles - errata 116 - first access is ignored memory write 0xA0000000 0xA0000000 ;access SDRAM memory write 0xA0000000 0xA0000000 ;access SDRAM memory write 0xA0000000 0xA0000000 ;access SDRAM memory write 0xA0000000 0xA0000000 ;access SDRAM memory write 0xA0000000 0xA0000000 ;access SDRAM memory write 0xA0000000 0xA0000000 ;access SDRAM memory write 0xA0000000 0xA0000000 ;access SDRAM memory write 0xA0000000 0xA0000000 ;access SDRAM memory write 0xA0000000 0xA0000000 ;access SDRAM memory read 0xA0000000 ;read SDRAM memory write 0x48000040 0x00320032 ;MDMRS ; ; Set up GPIOs ; GPIO_11 -> NAND CS ; mem write 0x40E00018 0xFFFFFFFF ; GPSR0 - GPIO Pin Output Set Register GPIO<31:0> mem write 0x40E0001C 0xFFFFFFFF ; GPSR1 - GPIO Pin Output Set Register GPIO<63:32> mem write 0x40E00020 0xFFFFFFFF ; GPSR2 - GPIO Pin Output Set Register GPIO<80:64> mem write 0x40E00118 0xFFFFFFFF ; GPSR3 - GPIO Pin Output Set Register GPIO<127:96> mem write 0x40E0000C 0xC021AA00 ; GPDR0 - GPIO Pin Direction Register GPIO<31:0>; set GPIO_11 as output mem write 0x40E00010 0xFC4F2B82 ; GPDR1 - GPIO Pin Direction Register GPIO<63:32> mem write 0x40E00014 0x6021FFFF ; GPDR2 - GPIO Pin Direction Register GPIO<95:64> mem write 0x40E00054 0x80000000 mem write 0x40E00058 0xA5000010 mem write 0x40E0005C 0x999A9558 mem write 0x40E00060 0xAAA00008 mem write 0x40E00064 0xAAAAAAAA mem write 0x40E00068 0x00000002 mem write 0x40E0006C 0x00000010 mem write 0x40E00070 0x00000008 ; set r11 0xA3000020 ;set frame pointer to free RAM memory write 0xA3000020 0xA3000028 ;dummy stack frame for GDB ; ; [FLASH_NOR] CHIP = TC58FVM5B2A ; flash chip ACCESS_METHOD = AGENT ; program method auto CHECK_ID = YES ; check chip ID CHIP_WIDTH = 16 ; chip is in 16 bit configuration CHIP_COUNT = 1 ; one chip is used BASE_ADDR = 0 ; chip is mapped at 0x0000000 FILE = "tftp:u-boot.bin", BIN, 0 ; file to program AUTO_ERASE = YES ; erase before program AUTO_LOCK = NO ; lock after program [FLASH_NAND] CHIP = NAND_FLASH ; flash device DATA_SHIFT = 16 ; NAND DATA_BUS[7..0] is connected to CPU's DATA_BUS[23..16] DATA_BASE = 0x04000000 ; data CMD_BASE = 0x04000004 ; commands (CLE) ADDR_BASE = 0x04000008 ; addreses (ALE) ; address and value for asserting the Nand Flash Chip select ; [addr] = value CS_ASSERT = 0x40E00024, 0x800 ; GPIO_11 = 0 ; address and value for releasing the Nand Flash Chip select ; [addr] = value CS_RELEASE = 0x40E00018, 0x800 ; GPIO_11 = 1 ;FILE = "tftp:jffs2_image.bin", BIN, 0 ; do not use TFTP if the file > 32MB FILE = "ftp://user:password@192.168.3.1/jffs2_image.bin", BIN, 0 ; list with bad blocks to be marked as bad ;========================================= ;BAD_BLOCKS=62 ; CAUTION!!! ; Enable erasing of bad blocks ; DO NOT Enable this if you don't know what you are doing ; For more information see the AN006 (www.ronetix.at/an006.html) ;ERASE_BAD_BLOCKS = YES OOB_INFO = JFFS2 ; how to deal with the oob (spare) info ; RAW - program 528/2112 bytes from file ; JFFS2 - program 512/2048 bytes from file and add ECC bytes ; FF - program 512/2048 bytes from file, the spare info is 0xFF [SERIAL] ; serial port configuration BAUD = 115200 STOP_BITS = 1 PARITY = NONE TCP_PORT = 0 ; enable CLI over RS232 ;TCP_PORT = 2023 ; enable serial over TCP/IP [TELNET] PROMPT = "cmx270> " ; telnet prompt ;BACKSPACE = 127 ; comment out for autodetect [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 25 ; beeper volume [ACTIONS] ; user defined scripts 1 = erase 2 = prog [erase] ; erase flash flash erase [prog] ; program flash flash program