;-------------------------------------------------------------------------- ; ; ; PEEDI target configuration file for PowerPC MPC8360 processor ; ; Ronetix ; ; Supported devices : PPC405GP ; ; Board : - ; ; Revision : 1.0 ; ; Date : April 6, 2010 ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. These licenses must be filled before using this file. ; The [LICENSE] section may contain license keys for one or more PEEDIs. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2010, 1111-1111-1111-1 ; KEY = XXXXX, 2222-2222-2222-2 ; ; The [LICENSE] section may point to an external file which contains ; license keys for one or more PEEDIs. The external file must include ; the text [LICENSE] followed by all keys. ; ; Example: ; [LICENSE] ; FILE = tftp://192.168.3.1/license.txt ; or ; FILE=eep:license.txt ; or ; FILE = ftp://user:password@192.168.3.1/license.txt ; ; ; PEEDI is shipped with license keys stored in "eep:license.txt" and ; printed on a label on the bottom side of PEEDI. ; [LICENSE] FILE=eep:license.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote REMOTE_PORT = 2000 ; TCP/IP port [TARGET] PLATFORM = PPC400 ; platform is MPC8300 [PLATFORM_PPC400] JTAG_CHAIN = 7 ; list of IR lenght of all TAP controller in JTAG chain JTAG_CLOCK = 4000, 25000 ; JTAG Clock in [kHz] - 10kHz jtag clock for init operations and 16MHz for normal work TRST_TYPE = PUSHPULL ; type of TRST output: OPENDRAIN or PUSHPULL RESET_TIME = 10 ; lenght of RESET pulse in ms; 0 means no RESET TIME_AFTER_RESET = 200 CORE0 = PPC405 CORE0_INIT = INIT_PPC405 CORE0_STARTUP_MODE = reset ; Reset Configuration words: Hi, Lo registers ; The bit order differs from the Freescale's User Manual: ; arg1 bit31 - PCIHOST ; arg1 bit30 - PCI64 ; arg1 bit29 - PCIARB ; .................... ; arg2 bit31 - LBCM ; arg2 bit30 - DDRCM ; .................. ; ; If you want to set RCWHR bit-0 (PCIHOST) and RCWLR bit-1 (DDRCM) regarding ; the Freescale's User Manual, you should use: CORE0_RCW = 0x80000000, 0x40000000 ; CORE0_BREAKMODE = hard ; breakpoint mode: CORE0_ENDIAN = big ; core is little endian CORE0_FLASH0 = FLASH_AM29LV040B CORE0_WORKSPACE = 0, 0x10000 ; length of workspace in bytes 1.5KB agent + 8KB data buffer (min. 2048(0x800) bytes) ; Default path to be used if only a file name (without the full path) is ; provided to a PEEDI command or for the FILE parameter in the Flash sections ; Examples: ; In a console: ; "flash prog tftp://192.168.3.1/image.elf" ; is equal to ; "flash prog image.elf" ; ; In a Flash Profile: ; FILE="tftp://192.168.3.1/image.bin", BIN, 0 ; is equal to ; FILE="image.bin", BIN, 0 ; CORE0_PATH = "tftp://192.168.3.1" ;CORE0_PATH = "card://" CORE0_FILE = "u-boot.bin", BIN, 0x0010000 ; default file [INIT_PPC405] ; init core register set spr 954 0x00000000 ;DCWR: Disable data cache write-thru set spr 1018 0x00000000 ;DCCR: Disable data cache set spr 1019 0x00000000 ;ICCR: Disable instruction cache set spr 982 0x00000000 ;EVPR: Exception Vector Table @0x00000000 ; Setup Peripheral Bus set dcr 18 0x00000010 ;Select PB0AP set dcr 19 0x9B015480 ;PB0AP: Flash and SRAM set dcr 18 0x00000000 ;Select PB0CR set dcr 19 0xFFF18000 ;PB0CR: 1MB at 0xFFF00000, r/w, 8bit set dcr 18 0x00000011 ;Select PB1AP set dcr 19 0x02815480 ;PB1AP: NVRAM and RTC set dcr 18 0x00000001 ;Select PB1CR set dcr 19 0xF0018000 ;PB1CR: 1MB at 0xF0000000, r/w, 8bit set dcr 18 0x00000012 ;Select PB2AP set dcr 19 0x04815A80 ;PB2AP: Keyboard and Mouse set dcr 18 0x00000002 ;Select PB2CR set dcr 19 0xF0118000 ;PB2CR: 1MB at 0xF0100000, r/w, 8bit set dcr 18 0x00000013 ;Select PB3AP set dcr 19 0x01815280 ;PB3AP: IRDA set dcr 18 0x00000003 ;Select PB3CR set dcr 19 0xF0218000 ;PB3CR: 1MB at 0xF0200000, r/w, 8bit set dcr 18 0x00000017 ;Select PB7AP set dcr 19 0x01815280 ;PB7AP: FPGA set dcr 18 0x00000007 ;Select PB7CR set dcr 19 0xF0318000 ;PB7CR: 1MB at 0xF0300000, r/w, 8bit ; Setup SDRAM Controller set dcr 16 0x00000080 ;Select SDTR1 set dcr 17 0x0086400D ;SDTR1: SDRAM Timing Register set dcr 16 0x00000040 ;Select MB0CF set dcr 17 0x00046001 ;MB0CF: 16MB @ 0x00000000 set dcr 16 0x00000048 ;Select MB2CF set dcr 17 0x01046001 ;MB2CF: 16MB @ 0x01000000 set dcr 16 0x00000030 ;Select RTR set dcr 17 0x05F00000 ;RTR: Refresh Timing Register set dcr 16 0x00000020 ;Select MCOPT1 set dcr 17 0x80800000 ;MCOPT1: Enable SDRAM Controller ; Setup MMU info mem wr 0x000000f4 0x00000000 ;invalidate kernel page table base mem wr 0x000000f8 0x00000000 ;invalidate process page table base mem wr 0x000000f0 0xc00000f4 ;invalidate page table base [FLASH_AM29LV040B] CHIP = AM29LV040B ; flash chip ACCESS_METHOD = AGENT ; program method auto CHECK_ID = YES ; check chip ID CHIP_WIDTH = 8 ; chip is in 16 bit configuration CHIP_COUNT = 1 ; one chip is used BASE_ADDR = 0xFFF80000 ; chip is mapped at 0xFFF80000 FILE = "u-boot.bin", BIN, 0xFFF80000 ; file to program AUTO_ERASE = NO ; erase before program AUTO_LOCK = NO ; lock after program [SERIAL] ; serial port configuration BAUD = 115200 STOP_BITS = 1 PARITY = NONE TCP_PORT = 0 [TELNET] PROMPT = "ppc405> " ; telnet prompt ;BACKSPACE = 127 ; comment out for autodetect [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 100 ; zummer volume [ACTIONS] ; user defined scripts 1 = erase 2 = prog [erase] ; erase flash flash erase [prog] ; program flash flash program