;-------------------------------------------------------------------------- ; ; ; PEEDI target configuration file for Freescale P4080 processor ; ; Ronetix GmbH ; ; Supported devices : Freescale P4080 ; ; Revision : 1.1 ; ; Date : April 4, 2012 ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. These licenses must be filled before using this file. ; The [LICENSE] section may contain license keys for one or more PEEDIs. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2010, 1111-1111-1111-1 ; KEY = XXXXX, 2222-2222-2222-2 ; ; The [LICENSE] section may point to an external file which contains ; license keys for one or more PEEDIs. The external file must include ; the text [LICENSE] followed by all keys. ; ; Example: ; [LICENSE] ; FILE = tftp://192.168.3.1/license.txt ; or ; FILE=eep:license.txt ; or ; FILE = ftp://user:password@192.168.3.1/license.txt ; ; ; PEEDI is shipped with license keys stored in "eep:license.txt" and ; printed on a label on the bottom side of PEEDI. ; [LICENSE] FILE = eep:license.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote REMOTE_PORT = 2000 ; TCP/IP port [TARGET] PLATFORM = QorIQ_P ; platform is QorIQ P series [PLATFORM_QorIQ_P] JTAG_CHAIN = 8 ; list of IR lenght of all TAP controller in JTAG chain JTAG_CLOCK = 7000 ; JTAG Clock in [kHz] - 10MHz jtag clock for Linux kernel debugging DBGREQ_OUTPUT = HIGH TRST_TYPE = PUSHPULL ; type of TRST output: OPENDRAIN or PUSHPULL RESET_TIME = 20 ; lenght of RESET pulse in ms; 0 means no RESET TIME_AFTER_RESET = 500 CORE0 = P4080A ; TAP is P1020 CPU ;CORE0_INIT = INIT_P4080 ; used to program code into FLASH CORE0_INIT = INIT_LINUX ; used to program code into FLASH CORE0_STARTUP_MODE = reset CORE0_BREAKMODE = soft ; breakpoint mode: CORE0_ENDIAN = big ; core is little endian CORE0_FLASH0 = NOR_FLASH CORE0_WORKSPACE = 0, 0x18000 ; workspace for flash programmer CORE0_FILE = "myfile.bin", BIN, 0x2000000 ; default file CORE0_PATH = "tftp://192.168.3.1/" ; default path CORE0_MMU_TRANS = 0xC0000000 ; used when CORE0_INIT = INIT_LINUX ;CORE0_MMU_PTBASE = 0 ; try kernel table MMU translation ;CORE0_PMEM_BASE = 0x20000000 ; physical memory base, if hosted by hypervisor CORE1 = P4080B ; TAP is P1020 CPU CORE1_STARTUP_MODE = run CORE1_BREAKMODE = soft ; breakpoint mode: CORE1_ENDIAN = big ; core is big endian CORE1_MMU_TRANS = 0xC0000000 ;CORE1_MMU_PTBASE = 0 CORE2 = P4080C CORE2_STARTUP_MODE = run CORE2_BREAKMODE = soft CORE2_ENDIAN = big CORE2_MMU_TRANS = 0xC0000000 ;CORE2_MMU_PTBASE = 0 CORE3 = P4080D CORE3_STARTUP_MODE = run CORE3_BREAKMODE = soft CORE3_ENDIAN = big CORE3_MMU_TRANS = 0xC0000000 ;CORE3_MMU_PTBASE = 0 CORE4 = P4080E CORE4_STARTUP_MODE = run CORE4_BREAKMODE = soft CORE4_ENDIAN = big CORE4_MMU_TRANS = 0xC0000000 ;CORE4_MMU_PTBASE = 0 CORE5 = P4080F CORE5_STARTUP_MODE = run CORE5_BREAKMODE = soft CORE5_ENDIAN = big CORE5_MMU_TRANS = 0xC0000000 ;CORE5_MMU_PTBASE = 0 CORE6 = P4080G CORE6_STARTUP_MODE = run CORE6_BREAKMODE = soft CORE6_ENDIAN = big CORE6_MMU_TRANS = 0xC0000000 ;CORE6_MMU_PTBASE = 0 CORE7 = P4080H CORE7_STARTUP_MODE = run CORE7_BREAKMODE = soft CORE7_ENDIAN = big CORE7_MMU_TRANS = 0xC0000000 ;CORE7_MMU_PTBASE = 0 [INIT_LINUX] break add hard 0xc06e048c go wait 20000 stop break del all beep 100 100 [INIT_P4080] ; Setup TLB1 ;1/1: fe000000->0_fe000000 16MB -I-G- RWXRWX set mas0 0x10010000 set mas1 0x80000700 set mas2 0xfe00000a set mas3 0xfe00003f set mas7 0x00000000 exec 0x4C00012C exec 0x7C0007A4 exec 0x4C00012C ;1/2: e0000000->0_e0000000 256MB -I-G- RWXRWX set mas0 0x10020000 set mas1 0x80000900 set mas2 0xe000000a set mas3 0xe000003f set mas7 0x00000000 exec 0x4C00012C exec 0x7C0007A4 exec 0x4C00012C ;1/3: 00000000->0_00000000 1GB ----- RWXRWX set mas0 0x10030000 set mas1 0x80000a00 set mas2 0x00000000 set mas3 0x0000003f set mas7 0x00000000 exec 0x4C00012C exec 0x7C0007A4 exec 0x4C00012C ;1/4: 40000000->0_40000000 1GB ----- RWXRWX set mas0 0x10040000 set mas1 0x80000a00 set mas2 0x40000000 set mas3 0x4000003f set mas7 0x00000000 exec 0x4C00012C exec 0x7C0007A4 exec 0x4C00012C ;1/5: 80000000->0_80000000 1MB ----- RWXRWX set mas0 0x10050000 set mas1 0x80000500 set mas2 0x80000000 set mas3 0x8000003f set mas7 0x00000000 exec 0x4C00012C exec 0x7C0007A4 exec 0x4C00012C ; Initialize LAWBAR's mem write 0xfe000c00 0x00000000 ;LAWBAR0 : Flash @0_e0000000 mem write 0xfe000c04 0xe0000000 mem write 0xfe000c08 0x81f0001b ;LAWAR0 : eLBC 256MB mem write 0xfe000c10 0x00000000 ;LAWBAR1 : CPC1/SRAM @0_80000000 mem write 0xfe000c14 0x80000000 mem write 0xfe000c18 0x81000013 ;LAWAR1 : DDR1/CPC1 1MB mem write 0xfe000df0 0x00000000 ;LAWBAR31: SDRAM @0_00000000 mem write 0xfe000df4 0x00000000 mem write 0xfe000df8 0x8100001e ;LAWAR31 : DDR1/CPC1 2GB ; Use L3 cache (CPC1) as SRAM at 0x80000000 mem write 0xfe010104 0x8000000b ;CPC1_SRCR0: all 32 ways as SRAM mem write 0xfe010000 0x80000000 ;CPC1_CSR0 : CPC enable mem write 0xfe010f00 0x08000000 ;CPC 4 Errata ; Local Bus Controller ;mem write 0xfe124004 0xf8000ff7 ;OR0: mem write 0xfe124004 0xf8000020 ;OR0: mem write 0xfe124000 0xe8001001 ;BR0: ;mem write 0xfe12400c 0xf8000ff7 ;OR1: mem write 0xfe12400c 0xf8000020 ;OR1: mem write 0xfe124008 0xe0001001 ;BR1: ; Setup DDR controller 1 mem write 0xfe008000 0x0000003f ;CS0_BNDS mem write 0xfe008008 0x0040007f ;CS1_BNDS mem write 0xfe008010 0x00000000 ;CS2_BNDS mem write 0xfe008018 0x00000000 ;CS3_BNDS mem write 0xfe008080 0x80014202 ;CS0_CONFIG mem write 0xfe008084 0x80014202 ;CS1_CONFIG mem write 0xfe008088 0x00000000 ;CS2_CONFIG mem write 0xfe00808C 0x00000000 ;CS3_CONFIG mem write 0xfe0080C0 0x00000000 ;CS0_CONFIG_2 mem write 0xfe0080C4 0x00000000 ;CS1_CONFIG_2 mem write 0xfe0080C8 0x00000000 ;CS2_CONFIG_2 mem write 0xfe0080CC 0x00000000 ;CS3_CONFIG_2 mem write 0xfe008100 0x01031000 ;TIMING_CFG_3 mem write 0xfe008104 0x55440804 ;TIMING_CFG_0 mem write 0xfe008108 0x74713a66 ;TIMING_CFG_1 mem write 0xfe00810C 0x0fb8911b ;TIMING_CFG_2 mem write 0xfe008110 0x47048000 ;DDR_CFG mem write 0xfe008114 0x24401011 ;DDR_CFG_2 mem write 0xfe008118 0x00421850 ;DDR_MODE mem write 0xfe00811C 0x00100000 ;DDR_MODE_2 mem write 0xfe008124 0x10400100 ;DDR_INTERVAL mem write 0xfe008128 0xdeadbeef ;DDR_DATA_INIT mem write 0xfe008130 0x03000000 ;DDR_CLK_CNTL mem write 0xfe008148 0x00000000 ;DDR_INIT_ADDR mem write 0xfe00814C 0x00000000 ;DDR_INIT_EXT_ADDR mem write 0xfe008160 0x00220001 ;TIMING_CFG_4 mem write 0xfe008164 0x03401500 ;TIMING_CFG_5 mem write 0xfe008170 0x89080600 ;DDR_ZQ_CNTL mem write 0xfe008174 0x8655a608 ;DDR_WRLVL_CNTL mem write 0xfe008B28 0x00000000 ;DDRCDR_1 mem write 0xfe008B2C 0x00000000 ;DDRCDR_2 wait 100 mem write 0xfe008110 0xc7048000 ;DDR_CFG wait 1000 ; Release cores for booting mem write 0xfe0E00E4 0x000000FF ;BRR: release all cores ; write DNH instruction to default vector mem write 0x00000000 0x4c00018c ;catch default vector [NOR_FLASH] ;CHIP = S29GL01GP CHIP = CFI_FLASH BASE_ADDR = 0xE8000000 ACCESS_METHOD = AGENT ;CHECK_ID = YES ;CHIP_WIDTH = 16 ;CHIP_COUNT = 1 FILE = "test32k.bin", BIN, 0xe0000000 [SERIAL] ; serial port configuration BAUD = 115200 STOP_BITS = 1 PARITY = NONE TCP_PORT = 0 [TELNET] PROMPT = "p4080> " ; telnet prompt ;BACKSPACE = 127 ; comment out for autodetect [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 100 ; zummer volume [ACTIONS] ; user defined scripts 1 = erase 2 = prog [erase] ; erase flash flash erase [prog] ; program flash flash program