;-------------------------------------------------------------------------- ; ; ; PEEDI target configuration file for PowerPC MPC8540 processor ; ; Ronetix GmbH ; ; Supported devices : MPC8540 ; ; Board : MicroSys PM854 ; ; Revision : 1.1 ; ; Date : May 12, 2010 ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. These licenses must be filled before using this file. ; The [LICENSE] section may contain license keys for one or more PEEDIs. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2010, 1111-1111-1111-1 ; KEY = XXXXX, 2222-2222-2222-2 ; ; The [LICENSE] section may point to an external file which contains ; license keys for one or more PEEDIs. The external file must include ; the text [LICENSE] followed by all keys. ; ; Example: ; [LICENSE] ; FILE = tftp://192.168.3.1/license.txt ; or ; FILE=eep:license.txt ; or ; FILE = ftp://user:password@192.168.3.1/license.txt ; ; ; PEEDI is shipped with license keys stored in "eep:license.txt" and ; printed on a label on the bottom side of PEEDI. ; [LICENSE] FILE=eep:license.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote REMOTE_PORT = 2000 ; TCP/IP port [TARGET] PLATFORM = MPC8500 ; platform is MPC8500 [PLATFORM_MPC8500] JTAG_CHAIN = 8 ; list of IR lenght of all TAP controller in JTAG chain JTAG_CLOCK = 8000 DBGREQ_OUTPUT = HIGH TRST_TYPE = PUSHPULL ; type of TRST output: OPENDRAIN or PUSHPULL RESET_TIME = 20 ; lenght of RESET pulse in ms; 0 means no RESET WAKEUP_TIME = 200 CORE0 = MPC8540 ; TAP is MPC8540 CPU ;CORE0_INIT = INIT_BOOT ; used to debug already programmed code CORE0_INIT = INIT_BOARD ; used to program code into FLASH ; Note: PM854 doesn't work with STARTUPMODE = LOOP ; in this case the board reboots permanently CORE0_STARTUP_MODE = RESET CORE0_BREAKMODE = soft ; breakpoint mode: CORE0_ENDIAN = big ; core is little endian CORE0_FLASH0 = FLASH_NOR CORE0_WORKSPACE = 0xF0000000, 0x10600 ; workspace for flash programmer CORE0_FILE = "myfile.bin", BIN, 0x2000000 ; default file CORE0_PATH = "tftp://192.168.3.60" ;CORE0_MMU_TRANS = 0xC0000000 ; used when CORE0_INIT = INIT_BOOT ;CORE0_MMU_PTBASE = 0xF0 ; [INIT_BOOT] ; Move the L2SRAM to the initial MMU page mem wr 0xFF720000 0x68010000 ;L2CTL (256k) mem wr 0xFF720100 0xFFFC0000 ;L2SRBAR0 (256k) mem wr 0xFF720000 0xA8010000 ;L2CTL (256k) ; Clear L2SRAM with DMA mem wr 0xFF721110 0x00040000 ;SATR0 SREADTTYPE=Read, don't snoop mem wr 0xFF721114 0xFF700004 ;SAR0 Dummy source register mem wr 0xFF721118 0x00050000 ;DATR0 DWRITETYPE=Write, snoop local processor mem wr 0xFF721120 0x00040000 ;BCR0 Size mem wr 0xFF721100 0x0f009404 ;MR0 BWC=f,SAHTS=2(4 bytes),SAHE=1,SWSM=Dest,SRW=1,CTM=1,CS=0 mem wr 0xFF72111c 0xFFFC0000 ;DAR0 which sets CS=1 wait 200 ;let DMA complete mem wr 0xFF721100 0x00000000 ;MR0 reset condition ; load and exec boot code (needed if STARTUP HALT) mem wr 0xFFFFFFFC 0x48000000 ;loop go halt set spr 63 0xFFFF0000 ;IVPR to boot core set spr 415 0x0000F000 ;IVOR15 : Debug exception ; Remove the L2SRAM from the initial MMU page mem wr 0xFF720000 0x28010000 ;L2CTL mem wr 0xFF720000 0x28000000 ;L2CTL [INIT_BOARD] ;---------------------------------------------------------------------- ; Standard Initialization Code for MicroSys PM854 miriac module ;---------------------------------------------------------------------- echo Move the L2SRAM to the initial MMU page mem wr 0xFF720000 0x68010000 ;L2CTL mem wr 0xFF720100 0xFFFC0000 ;L2SRBAR0 mem wr 0xFF720000 0xA8010000 ;L2CTL echo Clear L2SRAM with DMA mem wr 0xFF721110 0x00040000 ;SATR0 SREADTTYPE=Read, don't snoop mem wr 0xFF721114 0xFF700004 ;SAR0 Dummy source register mem wr 0xFF721118 0x00050000 ;DATR0 DWRITETYPE=Write, snoop local processor mem wr 0xFF721120 0x00040000 ;BCR0 Size mem wr 0xFF721100 0x0f009404 ;MR0 BWC=f,SAHTS=2(4 bytes),SAHE=1,SWSM=Dest,SRW=1,CTM=1,CS=0 mem wr 0xFF72111c 0xFFFC0000 ;DAR0 which sets CS=1 wait 200 ;let DMA complete mem wr 0xFF721100 0x00000000 ;MR0 reset condition ; load TLB entries, helper code @ 0xfffff000 mem wr 0xfffffff4 0x7c0007a4 ;tlbwe mem wr 0xfffffff8 0x7c0004ac ;msync mem wr 0xfffffffc 0x48000000 ;loop go halt ; CCSR echo 1MB TLB1 #1 0xe0000000 - 0xe00fffff set MAS0 0x10010000 set MAS1 0x80000500 set MAS2 0xe000000a set MAS3 0xe0000015 set MAS4 0x00000000 go 0xfffffff4 halt ; PCI echo 64 MB TLB1 #2 0xc0000000 - 0xc3ffffff set MAS0 0x10020000 set MAS1 0x80000800 set MAS2 0xc0000018 set MAS3 0xc0000015 go 0xfffffff4 halt ; DDR echo 256 MB TLB1 #3 0x00000000 - 0x0fffffff set MAS0 0x10030000 set MAS1 0x80000900 set MAS2 0x00000018 set MAS3 0x00000015 go 0xfffffff4 halt ; FLASH echo 16 MB TLB1 #4 0xfe000000 - 0xfeffffff set MAS0 0x10040000 set MAS1 0x80000700 set MAS2 0xFE000018 set MAS3 0xFE000015 go 0xfffffff4 halt ; FLASH echo 16 MB TLB1 #5 0xff000000 - 0xffffffff set MAS0 0x10050000 set MAS1 0x80000700 set MAS2 0xff000018 set MAS3 0xff000015 go 0xfffffff4 halt ; L2SRAM echo 16 MB TLB1 #0 0xf0000000 - 0xf0ffffff set MAS0 0x10000000 set MAS1 0x80000700 set MAS2 0xf0000008 set MAS3 0xf0000015 go 0xfffffff4 halt ; Remove the L2SRAM from the initial MMU page mem wr 0xFF720000 0x28010000 ;L2CTL mem wr 0xFF720000 0x28000000 ;L2CTL ; Move CCSRBAR to 0x40000000 mem wr 0xff700000 0x000e0000 ;CCSRBAR to 0x40000000 ; Initialize LAWBAR's mem wr 0xe0000C08 0x00000000 ;LAWBAR0 : @0x00000000 mem wr 0xe0000C10 0x80f0001b ;LAWAR0 : DDR/SDRAM 256MB mem wr 0xe0000C28 0x000c0000 ;LAWBAR1 : @0xc0000000 mem wr 0xe0000C30 0x8040001d ;LAWAR1 : Local Bus 1GB ; Setup DDR (PM854 , 256MB DDR) mem wr 0xe0002000 0x0000000f ;CS0_BNDS, size=0xf*16MB mem wr 0xe0002080 0x80000102 ;CS0_CONFIG, row=13, col=10 mem wr 0xe0002108 0x37344321 ;TIMING_CFG_1, cas-lat=2.5 mem wr 0xe000210C 0x00000800 ;TIMING_CFG_2, cas-lat+1, 4/8-wr-delay mem wr 0xe0002110 0x02000000 ;DDR_SDRAM_CFG, disabled no-ecc unbuff-ddr, 2T mode mem wr 0xe0002118 0x00000062 ;DDR_SDRAM_MODE, ext-mode=0, mode=62 mem wr 0xe0002124 0x03e80000 ;DDR_SDRAM_IVAL, ref=1115, precharge=256 wait 200 mem wr 0xe0002110 0xc2000000 ;DDR_SDRAM_CFG, ddr & self ref enabled, no ecc ; Setup Flash chip select mem wr 0xe0005000 0xfe001801 ;BR0 mem wr 0xe0005004 0xfe006ff7 ;OR0 ; Setup flash programming workspace in L2SRAM mem wr 0xe0020000 0x68010000 ;L2CTL mem wr 0xe0020100 0xf0000000 ;L2SRBAR0 mem wr 0xe0020000 0xA8010000 ;L2CTL set IVPR 0xf0000000 ;IVPR to workspace set IVOR15 0x0011500 ;IVOR15 : Debug exception mem wr 0xf0001500 0x48000000 ;write valid instruction [FLASH_NOR] CHIP = CFI_FLASH ;CHIP = 28F128J3 ; flash chip ACCESS_METHOD = AGENT ; program method auto CHECK_ID = YES ; check chip ID CHIP_WIDTH = 16 ; 2x16 chips used CHIP_COUNT = 2 ; to form 32bit BASE_ADDR = 0xFE000000 ; chip is mapped at 0xFE000000 FILE = "test512k.bin", BIN, 0xFE000000 ; file to program AUTO_ERASE = NO ; erase before program AUTO_LOCK = NO ; lock after program [SERIAL] ; serial port configuration BAUD = 115200 STOP_BITS = 1 PARITY = NONE TCP_PORT = 0 [TELNET] PROMPT = "pm854> " ; telnet prompt ;BACKSPACE = 127 ; comment out for autodetect [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 100 ; zummer volume [ACTIONS] ; user defined scripts 1 = erase 2 = prog [erase] ; erase flash flash erase [prog] ; program flash flash program