;-------------------------------------------------------------------------- ; ; ; PEEDI target configuration file for PowerPC MPC8309 processor ; ; Ronetix GmbH ; ; Supported devices : MPC8309 ; ; Board : TWR-MPC8309 ; Note: ; There is a bug in the software of PCF51JU128-64P and OBSEL is ; oscillating with 25MHz which makes the debugging impossible. ; To resolve the problem connect J16.pin4 to J16.pin2. ; ; Revision : 1.0 ; ; Date : October 20, 2017 ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. These licenses must be filled before using this file. ; The [LICENSE] section may contain license keys for one or more PEEDIs. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2010, 1111-1111-1111-1 ; KEY = XXXXX, 2222-2222-2222-2 ; ; The [LICENSE] section may point to an external file which contains ; license keys for one or more PEEDIs. The external file must include ; the text [LICENSE] followed by all keys. ; ; Example: ; [LICENSE] ; FILE = tftp://192.168.3.1/license.txt ; or ; FILE=eep:license.txt ; or ; FILE = ftp://user:password@192.168.3.1/license.txt ; ; ; PEEDI is shipped with license keys stored in "eep:license.txt" and ; printed on a label on the bottom side of PEEDI. ; [LICENSE] FILE=eep:license.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote REMOTE_PORT = 2000 [TARGET] PLATFORM = MPC8300 [PLATFORM_MPC8300] JTAG_CHAIN = 8 JTAG_CLOCK = 20000 TRST_TYPE = PUSHPULL RESET_TIME = 20 WAKEUP_TIME = 50 CORE0 = MPC8308 CORE0_INIT = INIT_MPC8309 CORE0_STARTUP_MODE = reset CORE0_BOOT_ADDR = 0x00000100 ; Reset Configuration words: Hi, Lo registers ; The bit order differs from the Freescale's User Manual: ; arg1 bit31 - PCIHOST ; arg1 bit30 - PCI64 ; arg1 bit29 - PCIARB ; .................... ; arg2 bit31 - LBCM ; arg2 bit30 - DDRCM ; .................. ; ; If you want to set RCWHR bit-0 (PCIHOST) and RCWLR bit-1 (DDRCM) regarding ; the Freescale's User Manual, you should use: CORE0_RCW = 0x80000000, 0x40000000 ; CORE0_RCW = 0x84600000, 0x04040000 ;override reset configuration words CORE0_MMU_PTBASE = 0x000000F0 CORE0_BREAKMODE = soft ; breakpoint mode: CORE0_ENDIAN = big CORE0_FLASH0 = FLASH_NOR CORE0_WORKSPACE = 0x00000000, 0x10000 ; workspace for flash programmer ; Default path to be used if only a file name (without the full path) is ; provided to a PEEDI command or for the FILE parameter in the Flash sections ; Examples: ; In a console: ; "flash prog tftp://192.168.3.1/image.elf" ; is equal to ; "flash prog image.elf" ; ; In a Flash Profile: ; FILE="tftp://192.168.3.1/image.bin", BIN, 0 ; is equal to ; FILE="image.bin", BIN, 0 ; CORE0_PATH = "tftp://192.168.3.60" ;CORE0_PATH = "card://" CORE0_FILE = "myfile.bin", BIN, 0x2000000 ; default file [INIT_MPC8309] ;setMMRBaseAddr 0xFF400000 set MBAR 0xFF400000 ; change internal MMR base from 0xff400000 (reset value) to 0xe0000000 mem wr 0xff400000 0xe0000000 ; IMMRBAR = 0xe0000000 ;setMMRBaseAddr 0xe0000000 set MBAR 0xe0000000 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; System Configuration - Local Access Windows ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; Local Bus Local Access Windows ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; WINDOW 0 - NOR FLASH mem wr 0xe0000020 0xfe000000 ; LBLAWBAR0 - begining at 0xfe000000 mem wr 0xe0000024 0x80000018 ; LBLAWAR0 - enable, size = 32MB ; DDR Local Access Windows ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; WINDOW 0 - 1st DDR SODIMM mem wr 0xe00000a0 0x00000000 ; DDRLAWBAR0 - begining at 0x00000000 mem wr 0xe00000a4 0x8000001a ; DDRLAWAR0 - enable, size = 128MB ;********************************* ; DDR2 Controller Registers ;********************************* ;DDRCDR mem wr 0xE0000128 0x73000002 ; DDR_SDRAM_CLK_CNTL ; CLK_ADJST = b'010' ; 2 Clocks mem wr 0xE0002130 0x02000000 ; CS0_BNDS ; SA0 = b'000000000000' ; EA0 = b'000000000111' mem wr 0xE0002000 0x00000007 ;; 128MB ; CS0_CONFIG ; CS_0_EN = b'1' ; AP_0_EN = b'1' ; ODT_RD_CFG = b'0' ; ODT_WR_CFG = b'1' ; BA_BITS_CS_0 = b'00' ; ROW_BITS_CS_0 = b'001' ; 13 row bits ; COL_BITS_CS_0 = b'010' ; 10 columns bits mem wr 0xE0002080 0x80840102 ; TIMING_CFG_3 ; EXT_REFREC = b'000' ; 0 Clocks mem wr 0xE0002100 0x00000000 ; TIMING_CONFIG_1 ; bit 1-3 = 2 - PRETOACT precharge activate interval 2 clock cycles ; bit 4-7 = 6 - ACTTOPRE activate to precharge interval 6 clock cycles ; bit 9-11 = 2 = ACTTORW activate to r/w interval 2 clock cycles ; bit 13 - 15 = 5 - CASLAT CAS latency 3 clock cycles ; bit 16 - 19 = 6 - REFREC refresh recovery time 14 clock cycles ; bit 21 - 23 = 2 - WRREC data to precharge interval 2 clock cycles ; bit 25 - 27 = 2 - ACTTOACT activate to activate interval 2 clock cycles ; bit 29 - 31 = 2 - WRTORD write data to read command interval 2 clock cycles mem wr 0xe0002108 0x26256222 ; TIMING_CONFIG_2 ; bit 19-21 = b010 - WR_DATA_DELAY - 1/2 DRAM clock delay mem wr 0xe000210C 0x0f9028c7 ; TIMING_CFG_0 ; RWT = b'00' ; 0 Clocks ; WRT = b'00' ; 0 Clocks ; RRT = b'00' ; 0 Clocks ; WWT = b'00' ; 0 Clocks ; ACT_PD_EXIT = b'010' ; 2 Clocks ; PRE_PD_EXIT = b'010' ; 2 Clocks ; ODT_PD_EXIT = b'1000' ; 8 Clocks ; MRS_CYC = b'0010' ; 2 Clocks mem wr 0xE0002104 0x00220802 ; DDR_SDRAM_CFG ; MEM_EN = b'0' ; SREN = b'1' ; RD_EN = b'0' ; SDRAM_TYPE = b'011' ; DYN_PWR = b'0' ; 32_BE = b'1' ; 8_BE = b'0' ; NCAP = b'0' ; 2T_EN = b'0' ; x32_EN = b'0' ; PCHB8 = b'0' ; HSE = b'0' ; MEM_HALT = b'0' ; BI = b'0' mem wr 0xE0002110 0x43080000 ; DDR_SDRAM_CFG_2 ; FRC_SR = b'0' ; DQS_CFG = b'00' ; ODT_CFG = b'10' ; NUM_PR = b'0001' ; D_INIT = b'0' mem wr 0xE0002114 0x00401000 ; DDR_SDRAM_MODE ; Extended Mode Register: Outputs=0 or 1? ; Mode Register mem wr 0xE0002118 0x44400232 ; DDR_SDRAM_MODE_2 ; Extended Mode Register 2 ; Extended Mode Register 3 mem wr 0xE000211C 0x8000c000 ; DDR_SDRAM_INTERVAL ; REFINT = 800 Clocks ; BSTOPRE = 100 Clocks mem wr 0xE0002124 0x03200064 ;delay before enable wait 300 ;Enable: DDR_SDRAM_CFG mem wr 0xE0002110 0xc3080000 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; Local Bus Interface (LBIU) Configuration ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; CS0 - 8MB NOR FLASH mem wr 0xe0005000 0xfe001001 ; BR0 base address at 0xFF800000, port size 16 bit, GPCM, valid ;mem wr 0xe0005000 0xfe001001 ; BR0 base address at 0xFE000000, port size 16 bit, GPCM, valid mem wr 0xe0005004 0xfe000ff7 ; OR0 8MB flash size, 15 w.s., timing relaxed ; LBCR - local bus enable mem wr 0xe00050d0 0x00000000 ; LCRR ; bit 14 - 15 = 0b11 - EADC - 3 external address delay cycles ; bit 28 - 31 = 0x0010 - CLKDIV - system clock:memory bus clock = 2 mem wr 0xe00050d4 0x00030002 ;;;mem wr 0xe00050d4 0x00010002 set MSR 0x2000 ; FP available, machine check disable, exception vectors at 0x0000_0000 mem wr 0xE0000800 0x00000000 ; ACR - Enable Core [FLASH_NOR] CHIP = CFI_FLASH ACCESS_METHOD = AGENT ; program method auto CHIP_WIDTH = 16 ; chip is in 16 bit configuration CHIP_COUNT = 1 ; one chip is used BASE_ADDR = 0xFE000000 ; chip is mapped at 0xFE000000 FILE = "test512k.bin" BIN 0xFF800000 [SERIAL] BAUD = 115200 STOP_BITS = 1 PARITY = NONE TCP_PORT = 0 [TELNET] PROMPT = "mpc8309> " ; telnet prompt [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 100 ; zummer volume [ACTIONS] ; user defined scripts 1 = erase 2 = prog 3 = verify [erase] flash erase [prog] flash program u_boot.bin bin 0 [verify] flash verify u-boot.bin 0