;-------------------------------------------------------------------------- ; ; ; PEEDI sample target configuration file ; ; Ronetix ; ; Supported devices : Vitesse VSC7428 ; ; Revision : 1.0 ; ; Date : July 5, 2013 ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. ; ; These licenses must be filled before using this file. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2007, 1111-1111-1111-1 ; KEY = CORTEXM3, 2222-2222-2222-2 ; ; The minimum required licenses are provided when PEEDI is purchased and ; are printed on the bottom side of PEEDI. ; [LICENSE] FILE = eep:license.txt [DEBUGGER] PROTOCOL = gdb_remote ; gdb remote REMOTE_PORT = 2000 ; TCP/IP port [TARGET] PLATFORM = MIPS32 ; platform is MIPS32 [PLATFORM_MIPS32] JTAG_CHAIN = 5 ; list of TAP controllers in the JTAG chain JTAG_CLOCK = 100, 5000 ; JTAG Clock in [kHz] 100,25000 TRST_TYPE = PUSHPULL ; type of TRST output: OPENDRAIN or PUSHPULL RESET_TIME = 100 ; length of RESET pulse in ms; 0 means no RESET WAKEUP_TIME = 100 ; time after the RESET to stabilize CORE0 = MIPS32_24K ; TAP is MIPS32_24K CPU CORE0_STARTUP_MODE = RESET ; stop the core immediately after reset CORE0_ENDIAN = LITTLE ; core is little endian CORE0_BREAKMODE = SOFT ; breakpoint mode CORE0_INIT = INIT_MIPS ; init section for MIPS32 CORE0_FLASH0 = FLASH_SPI ; FLASH by toggling the outputs CORE0_WORKSPACE = 0x20000000, 0x10000 [INIT_MIPS] ; -------------------- ; -------------------- ; GENERAL CPU SETTINGS ; -------------------- ; -------------------- ; Set Frequency to 416.66MHz ; Register HSIO:PLL5G_CFG ; Bits 11:6: ; (Other Bits must be set to defaults) ; 5 (default): 250MHz; 6: 416.66MHz; 14: 312.50MHz ; 5: 0x73B6F145 ; 6: 0x73B6F185 <-- use this ; 14: 0x73B6F385 mem wr 0x600A0000 0x73B6F185 ; Set Chip in normal mode ; Regoster ICPU_CFG:CPU_SYSTEM_CTRL:GENERAL_CTRL ; Bit 0: ; BOOT_MODE_ENA ; 1 = Boot Mode (Memory Map to PI) ; 0 = Normal Mode (Memory Map to DRAM) <-- use this mem wr 0x70000024 0x00000000 ; ----------------- ; ----------------- ; SPI CONFIGURATION ; ----------------- ; ----------------- ; SPI Timing Register ; Register ICPU_CFG:SPI_MST:SPI_MST_CFG ; Bits 4:0: ; CLK_DIV = 0x1F ; Bits 9:5: ; CS_DESELECT_TIME = 0x1F mem wr 0x70000050 0x000003FF ; SPI SW Mode Register ; Register ICPU_CFG:SPI_MST:SW_MODE mem wr 0x70000064 0x00003A02 ; Software SPI, OE enabled, DO low, SCK high ; -------------------- ; -------------------- ; INIT DRAM CONTROLLER ; -------------------- ; -------------------- ; ----- ; RESET ; ----- ; Put RAM Controller and PHYs into Reset mem or 0x70000278 0x00000001 ; PHYs mem or 0x70000020 0x00000001 ; Controller ;wait 100 ; Drop Reset of RAM Controller and PHYs mem and 0x70000020 0xFFFFFFFE ; Controller mem wr 0x70000278 0x00000002 ; PHYs (+ enable SSTL for PHYs) ; ---- ; PHYs ; ---- ; Set impedance to 60 ohms and enable SSTL mem wr 0x70000294 0x000000EF ; Set ODT, CK, CL Output Enable mem or 0x70000278 0x0000001C ; ------------ ; RAM SETTINGS ; ------------ ; MEMCTRL_CFG ; Burst size = 8 bytes ; Burst length = 8 ; 8 banks ; 14 Bits RAS ; 10 Bits CAS mem wr 0x70000238 0x000003D9 ; Set Refresh period to 1625 cycles, 1 pending refresh mem wr 0x70000240 0x00010659 ; ----------------- ; TIMING PARAMETERS ; ----------------- ; MEMCTRL_TIMING0: ; RD_TO_WR_DLY = 4 (suggested value) ; RAS_TO_PRECH_DLY = 13 ; WR_TO_PRECH_DLY = 10 ; RD_TO_PRECH_DLY = 3 ; WR_DATA_XFR_DLY = 1 ; RD_DATA_XFR_DLY = 1 ; ; MEMCTRL_TIMING1: ; RAS_TO_RAS_SAME_BANK_DLY = 11 ; BANK8_FAW_DLY = 7 ; PRECH_TO_RAS_DLY = 3 ; RAS_TO_RAS_DLY = 1 ; RAS_TO_CAS_DLY = 3 ; WR_TO_RD_DLY = 8 ; ; MEMCTRL_TIMING2: ; PRECH_ALL_DLY = 3 ; MDSET_DLY = 1 ; REF_DLY = 26 ; FOUR_HUNDRED_NS_DLY = 84 ; ; MEMCTRL_TIMING3: ; ODT_WR_DLY = 3 ; LOCAL_ODT_RD_DLY = 3 ; WR_TO_RD_CS_CHANGE_DLY = 3 mem wr 0x70000248 0x4328A311 mem wr 0x7000024C 0x0B073138 mem wr 0x70000250 0x311A0054 mem wr 0x70000254 0x00000333 ; --------------------- ; MEMORY MODE REGISTERS ; --------------------- ; MEMCTRL_MR0_VAL: ; Burst Length = 8 ; Burst Type = sequential ; Latency (CL) = 4 ; Mode = Normal Mode ; DLL Reset = No ; Write Recovery = 4 ; PD Mode = Fast exit (normal) ; ; MEMCTRL_MR1_VAL: ; DLL = Enabled (normal) ; ODS = Reduced ; RTT = Disabled ; Posted CAS# Additive Latency (AL) = 0 ; OCD Program = Enable OCD defaults ; DQS# = Enabled ; RDQS = Disabled ; Outputs = Enabled ; Mode Register = EMR ; ; MEMCTRL_MR2_VAL: ; SRT Enable = 1x refresh rate (0°C to 85°C) ; Mode Register = EMR2 ; ; MEMCTRL_MR3_VAL: ; Mode Register = EMR3 mem wr 0x70000258 0x00000643 mem wr 0x7000025C 0x00000382 mem wr 0x70000260 0x00000000 mem wr 0x70000264 0x00000000 ; ----------- ; TERMINATION ; ----------- ; MEMCTRL_TERMRES_CT ; ODT_WR_EXT = 0 ; ODT_WR_ENA = 0 ; LOCAL_ODT_RD_EXT = 0 ; LOCAL_ODT_RD_ENA = 0 mem wr 0x70000268 0x00000000 ; ----------- ; DATA STROBE ; ----------- ; MEMCTRL_DQS_DLY ; RESERVED (MUST BE SET TO ITS DEFAULTS = 0x3) = 3 ; RESERVED (MUST BE SET TO ITS DEFAULTS = 0x3) = 3 ; DQS_DLY = 6* 1/4 clock cycles mem wr 0x70000270 0x00000366 ; ---------------------------- ; INITIALIZE MEMORY CONTROLLER ; ---------------------------- ; MEMCTRL_CTRL ; STALL_REF_ENA = 0 ; INITIALIZE = 1 mem wr 0x70000234 0x00000001 [FLASH_SPI] CHIP = SPI25_FLASH ; SPI Flash chip CPU = GENERIC_SPI CS_ASSERT = 0x70000064 or 0x00000020 ; clear SI_nEn0 CS_RELEASE = 0x70000064 and 0xFFFFFFDF ; set SI_nEn0 SCLK_CLR = 0x70000064 or 0x00001000 ; set SPI_SCK high SCLK_SET = 0x70000064 and 0xFFFFEFFF ; set SPI_SCK low MOSI_SET = 0x70000064 or 0x00000400 ; set SPI_SDO MOSI_CLR = 0x70000064 and 0xFFFFFBFF ; clear SPI_SDO MISO_READ = 0x70000064 and 0x00000001 ; get SPI_SDI FILE = tftp://192.168.10.1/tito/uboot.bin, bin, 0 ; file to program AUTO_ERASE = NO ; erase before program [SERIAL] ; serial port configuration BAUD = 115200 STOP_BITS = 1 PARITY = NONE TCP_PORT = 0 [TELNET] PROMPT = "vsc> " ; telnet prompt ;BACKSPACE = 127 ; comment out for autodetect [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 25 ; beeper volume [ACTIONS] ; user defined scripts ;AUTORUN = 2 ; executed on every target connect 1 = prog [prog] flash erase flash prog