;-------------------------------------------------------------------------- ; ; ; PEEDI sample target configuration file ; ; Ronetix ; ; Supported devices : STM32 ; ; Revision : 1.5 ; ; Date : December 8, 2010 ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. These licenses must be filled before using this file. ; The [LICENSE] section may contain license keys for one or more PEEDIs. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2010, 1111-1111-1111-1 ; KEY = XXXXX, 2222-2222-2222-2 ; ; The [LICENSE] section may point to an external file which contains ; license keys for one or more PEEDIs. The external file must include ; the text [LICENSE] followed by all keys. ; ; Example: ; [LICENSE] ; FILE = tftp://192.168.3.1/license.txt ; or ; FILE=eep:license.txt ; or ; FILE = ftp://user:password@192.168.3.1/license.txt ; ; ; PEEDI is shipped with license keys stored in "eep:license.txt" and ; printed on a label on the bottom side of PEEDI. ; [LICENSE] FILE=eep:license.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote ; gdb remote REMOTE_PORT = 2000 ; TCP/IP port GDB_READ_INGNORE_TIME = 3000 [TARGET] PLATFORM = CortexM3_SWD ; platform is CortexM3 [PLATFORM_CortexM3_SWD] SWD_CLOCK = 100, 5000 ; SWD Clock in [kHz] TRST_TYPE = OPENDRAIN ; type of TRST output: OPENDRAIN or PUSHPULL RESET_TIME = 20 ; length of RESET pulse in ms; 0 means no RESET CORE0 = CortexM3 ; TAP is CortexM3 CPU CORE0_STARTUP_MODE = RESET ; stop the core immediately after reset CORE0_ENDIAN = LITTLE ; core is little endian CORE0_BREAKMODE = HARD ; breakpoint mode CORE0_INIT = INIT_STM32 ; init section for STM32 CORE0_FLASH = FLASH_STM32 ; FLASH section parameters CORE0_WORKSPACE = 0x20000000, 0x4000 ; workspace for agent programming ;CORE0_SWO = 0, 2001 [INIT_STM32] mem or 0x40021000 0x00010000 ; switch On HSE wait 100 ; wait to stabilize mem wr 0x40021004 0x001D0000 ; config PLL div:1 mul:9 = 72MHz mem or 0x40021000 0x01000000 ; switch On PLL wait 100 ; wait to stabilize mem wr 0x40022000 0x00000012 ; 1ws for FLASH mem wr 0x40021004 0x001D0002 ; select PLL ; init SWO mem wr 0xE0042004 0x20 ; en. async trace mem wr 0xE0040010 1 ; SWO prescaler 0 mem wr 0xE00400F0 1 ; en. Manchester encoding mem wr 0xE0040304 0 ; bypass formatter mem wr 0xE0000FB0 0xC5ACCE55 ; unlock access to ITM registers mem wr 0xE0000E80 0x10009 ; trace ID = 1, ITM and DTW enabled mem wr 0xE0000E40 0xF ; en. all tracing ports mem wr 0xE0000E00 0xFFFFFFFF ; en. all stimulus ports [FLASH_STM32] CHIP = STM32 ; flash chip BASE_ADDR = 0x0 ; flash is mapped at 0 ACCESS_METHOD = AGENT ; use agent programming FILE = "tftp://192.168.0.1/myfile.bin" 0x8000000 ; file to program [SERIAL] ; serial port configuration BAUD = 115200 STOP_BITS = 1 PARITY = NONE TCP_PORT = 0 [TELNET] PROMPT = "stm32> " ; telnet prompt ;BACKSPACE = 127 ; comment out for autodetect [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 25 ; beeper volume [ACTIONS] ; user defined scripts ;AUTORUN = 2 ; executed on every target connect 1 = erase 2 = prog 3 = dump_ram 4 = dump_flash [erase] ; erase flash flash erase [prog] ; program flash flash prog [dump_ram] ; dump RAM memory dump 0x20000000 0x5000 tftp://192.168.0.1/ram.bin [dump_flash] ; dump FLASH memory dump 0x00000000 0x20000 tftp://192.168.0.1/flash.bin