;-------------------------------------------------------------------------- ; ; ; PEEDI sample target configuration file ; ; Ronetix GmbH ; ; Supported devices : Atmel SAMV71-XULT ; ; Revision : 1.0 ; ; Date : February 18, 2016 ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. These licenses must be filled before using this file. ; The [LICENSE] section may contain license keys for one or more PEEDIs. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2010, 1111-1111-1111-1 ; KEY = XXXXX, 2222-2222-2222-2 ; ; The [LICENSE] section may point to an external file which contains ; license keys for one or more PEEDIs. The external file must include ; the text [LICENSE] followed by all keys. ; ; Example: ; [LICENSE] ; FILE = tftp://192.168.3.1/license.txt ; or ; FILE=eep:license.txt ; or ; FILE = ftp://user:password@192.168.3.1/license.txt ; ; ; PEEDI is shipped with license keys stored in "eep:license.txt" and ; printed on a label on the bottom side of PEEDI. ; [LICENSE] FILE = eep://license.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote ; gdb remote REMOTE_PORT = 2000 ; TCP/IP port FLASH = FLASH_SAMV71 [TARGET] PLATFORM = CortexM3_SWD ; platform is ARM [PLATFORM_CortexM3_SWD] SWD_CLOCK = 100, 12000 ; SWD Clock in [kHz] RESET_TIME = 0 ; length of RESET pulse in ms; 0 means no RESET CORE0 = Cortex-M ; auto detected CORE0_RESET_MODE = sysresetreq ; software reset: sysresetreq or vectreset CORE0_STARTUP_MODE = RESET ; stop the core immediately after reset CORE0_ENDIAN = LITTLE ; core is little endian CORE0_BREAKMODE = HARD, 0x00400000, 0x00600000 ; breakpoint mode CORE0_WORKSPACE = 0x20400000, 0x10000 CORE0_INIT = INIT_SAMV71 ; init section CORE0_FLASH = FLASH_SAMV71 ; FLASH section parameters CORE0_PATH = "tftp://192.168.3.1/samv7/" CORE0_SWO = 0,2002 [INIT_SAMV71] ; User Reset Enable memory w32 0x400E1808 0xA5000001 ; RSTC_MR -> user reset enable ; ----------------------------- ; ----------- Clock ----------- ; ----------------------------- ; Clock Settings (500MHz PLL VDDIO 3.3V and VDDCORE 1.2V) ; Clock Settings (300MHz HCLK, 150MHz MCK)=> PRESC = 1, MDIV = 2 ; Oscillator ; 3: 0x01 [1] MOSCSEL Main Oscillator Selection (0=RC, 1=Crystal) ; 3: 0x04 [1] XT32KFME Slow Crystal Oscillator Frequency Monitoring Enable ; 2: 0x37 [8] KEY ; 1: 0x00 [8] MOSCXTST Main Crystal Oscillator Start-up Time (number of slow clock cycles * 8) ; 0: 0x01 [1] MOSCXTEN Main Crystal Oscillator Enable ; -- ; 0x00000028 - reset value ; 0x08 [1] MOSCRCEN Main On-Chip RC Oscillator Enable ; 0x20 [3] MOSCRCF Main On-Chip RC-Oscillator Frequency Selection {Bit 4-6} memory w32 0x400E0620 0x04370029 ; CKGR_MOR -> enable main oscillator wait 10 ; select XTAL 32k Crystal ; KEY = 0xA5 memory w32 0x400E1810 0xA5000008 ; SUPC_CR wait 10 ; init main oscillator memory w32 0x400E0620 0x00370809 ; CKGR_MOR init wait 10 ; switch to XTAL memory w32 0x400E0620 0x01370809 ; CKGR_MOR -> select Crystal (MOSCXTST=8) wait 10 ; select Main CLK memory w32 0x400E0630 0x00000001 ; PMC_MCKR -> Master Clock Source Selection: CSS = Main_CLK wait 10 ; PMC CLock Generator PLLA ; Bit 29 = ONE ; Bit 16 - 26 = MULA : 0x18 ; Bit 8-13 = PLLACOUNT : 0x3F ; Bit 0-7 = DIVA : 0x1 Divider is bypassed and PLLA is enabled memory w32 0x400E0628 0x20183F01 ; CKGR_PLLAR12*25 wait 10 ; wait 10ms ; switch to PLLA ; Bit 8-9 = MDIV : PCK_DIV2 = 1 -> Prescaler/2 ; Bit 4-6 = PRES : Processor Clock Prescaler = CLK_1 = 0 -> Prescaler 1 ; Bit 0-1 = CSS : 2 = PLLA_CLK ; ; XTAL-Crystal = 12M * (MULA + 1) = 12M * 25 = 300MHz memory w32 0x400E0630 0x00000101 ; PMC_MCKR set prescaler first wait 25 memory w32 0x400E0630 0x00000102 ; PMC_MCKR switch to PLLA wait 25 ; set Flash wait states memory w32 0x400E0C00 0x00000500 ; 4 Wait states wait 10 mem write 0xE000ED88 0xF00000 ; enable FPU ;; Init ITM ;[init_itm] mem wr 0xE0000000 0x41424344 ;ITM.[0] Send Data via ITM ; -------- SDRAM - 2MiB at 0x70000000 ------ ;[INIT_SDRAM] ; ATSAMV71-XULT ; SD-RAM: ISSI IS42S16100E-7BLI, 512Kx16x2, 10ns (2MiB at 0x70000000) ; --> enable SMC! -> ID = 9 ; mem w32 0x400E0610 0x00000200 ; PMC_PCER0, PMC Peripheral Clock Enable Register 0 ; --> enable SMC + PIO_ABC mem w32 0x400E0610 0x00001e00 ; PMC_PCER0, PMC Peripheral Clock Enable Register 0 ; PIOA = 10 ; PIOB = 11 ; PIOC = 12 ; PIOD = 16 ; PIOE = 17 ; Set Pins ; -- PIO -- ; PERIPHERAL_A mem and32 0x400e1270 0xffffff00 mem and32 0x400e1274 0xffffff00 mem w32 0x400e1204 0x000000ff ; PERIPHERAL_A mem and32 0x400e1670 0xffffffc0 mem and32 0x400e1674 0xffffffc0 mem w32 0x400e1604 0x0000003f ; PERIPHERAL_A mem and32 0x400e0e70 0xfffe7fff mem and32 0x400e0e74 0xfffe7fff mem w32 0x400e0e04 0x00018000 ; PERIPHERAL_A mem and32 0x400e1270 0xc00fffff mem and32 0x400e1274 0xc00fffff mem w32 0x400e1204 0x3ff00000 ; PERIPHERAL_C mem and32 0x400e1470 0xffffdfff mem or32 0x400e1474 0x00002000 mem w32 0x400e1404 0x00002000 ; PERIPHERAL_C mem and32 0x400e0e70 0xffefffff mem or32 0x400e0e74 0x00100000 mem w32 0x400e0e04 0x00100000 ; PERIPHERAL_C mem and32 0x400e1470 0xfffdffff mem or32 0x400e1474 0x00020000 mem w32 0x400e1404 0x00020000 ; PERIPHERAL_C mem and32 0x400e1470 0xfffeffff mem or32 0x400e1474 0x00010000 mem w32 0x400e1404 0x00010000 ; PERIPHERAL_C mem and32 0x400e1470 0xffffbfff mem or32 0x400e1474 0x00004000 mem w32 0x400e1404 0x00004000 ; PERIPHERAL_C mem and32 0x400e1470 0xff7fffff mem or32 0x400e1474 0x00800000 mem w32 0x400e1404 0x00800000 ; PERIPHERAL_A mem and32 0x400e1270 0xffff7fff mem and32 0x400e1274 0xffff7fff mem w32 0x400e1204 0x00008000 ; PERIPHERAL_A mem and32 0x400e1270 0xfffbffff mem and32 0x400e1274 0xfffbffff mem w32 0x400e1204 0x00040000 ; PERIPHERAL_C mem and32 0x400e1470 0xffff7fff mem or32 0x400e1474 0x00008000 mem w32 0x400e1404 0x00008000 ; PERIPHERAL_C mem and32 0x400e1470 0xdfffffff mem or32 0x400e1474 0x20000000 mem w32 0x400e1404 0x20000000 ; PMC: Enable Peripheral Clock SD-RAM-Controller ; ID_SDRAMC = 62, >= 32 -> 62-32=30.Bit in PCER1 mem w32 0x400E0700 0x40000000 ; PMC_PCER1, PMC Peripheral Clock Enable Register 1 ; AHB Bus Matrix: SMC NAND Flash Chip Select Configuration Register ; Enable SDRAM (SDRAMEN bit 4) mem w32 0x40088124 0x00000010 ; CCFG_SMCNFCS ; Configure SD-RAM-Controller ; ( 1) SDRAMC_CR Config Register ; NC = COL8 = 8 bits : 0 | 2 ; NR = ROW11 = 12 row bits (4k) : 0 | 2 ;- ; NB = BANK2 = 2 Banks : 0 | 1 ; CAS = CL3 : 2 | 2 ; DBW Data Bus Width always 16 : 1 | 1 ;- ; TWR = 4 : 4 | 4 ; TRC_TRFC = 11 (63ns) : 11 | 4 ; TRP = 5 (21ns) : 5 | 4 ; TRCD = 5 (21ns) : 5 | 4 ; TRAS = 8 (42ns) : 8 | 4 ; TXSR = 13 (70ns) : 13 | 4 mem w32 0x40084008 0xD855B4C0 ; SDRAMC_CR ; ( 2) Memory Device Register = SDRAM mem w32 0x40084024 0x00000000 ; SDRAMC_MDR ; ( 3) pause wait 100 ; ( 4) NOP: 1 to Mode Field in SDRAMC_MR mem w32 0x40084000 0x00000001 ; SDRAM_MR NOP ; ( 5) write to abitrary address in SD-RAM mem w16 0x70000000 0x00 ; SDRAM-BASE wait 10 ; ( 6) 2 to Mode Field in SDRAMC_MR mem w32 0x40084000 0x00000002 ; SDRAM_MR ALLBANKS_PRECHARGE ; ( 7) write to abitrary address in SD-RAM mem w16 0x70000000 0x00 ; SDRAM-BASE wait 10 ; ( 8) 4 to Mode Field; ; write to abitrary address in SD-RAM _8_ times ; .1 mem w32 0x40084000 0x00000004 ; SDRAM_MR AUTO_REFRESH mem w16 0x70000000 0x01 ; SDRAM-BASE ; .2 mem w32 0x40084000 0x00000004 ; SDRAM_MR AUTO_REFRESH mem w16 0x70000000 0x02 ; SDRAM-BASE ; .3 mem w32 0x40084000 0x00000004 ; SDRAM_MR AUTO_REFRESH mem w16 0x70000000 0x03 ; SDRAM-BASE ; .4 mem w32 0x40084000 0x00000004 ; SDRAM_MR AUTO_REFRESH mem w16 0x70000000 0x04 ; SDRAM-BASE ; .5 mem w32 0x40084000 0x00000004 ; SDRAM_MR AUTO_REFRESH mem w16 0x70000000 0x05 ; SDRAM-BASE ; .6 mem w32 0x40084000 0x00000004 ; SDRAM_MR AUTO_REFRESH mem w16 0x70000000 0x06 ; SDRAM-BASE ; .7 mem w32 0x40084000 0x00000004 ; SDRAM_MR AUTO_REFRESH mem w16 0x70000000 0x07 ; SDRAM-BASE ; .8 mem w32 0x40084000 0x00000004 ; SDRAM_MR AUTO_REFRESH mem w16 0x70000000 0x08 ; SDRAM-BASE wait 10 ; ( 9) 3 to Mode Field; mem w32 0x40084000 0x00000003 ; SDRAM_MR LOAD_MODEREG ; (10) write to address in SD-RAM 0x70000000 mem w16 0x70000022 0xCAFE ; SDRAM-BASE + 0x22 wait 10 ; (11) 0 to Mode Field; mem w32 0x40084000 0x00000000 ; SDRAM_MR NORMAL ; (12) write to abitrary address in SD-RAM mem w16 0x70000000 0x00 ; SDRAM-BASE wait 10 ; (13) write refresh time in SDRAMC_TR ; (32 * (BOARD_MCK_FREQUENCY / 1000)) / 2048 ; MCK = 150000000 (150MHz) mem w32 0x40084004 0x00000927 ; SDRAMC_TR = 2343 ; (14) enable support for unaligned access (AXI) ; TMRD = 2 ; UNAL = 1 mem w32 0x40084028 0x00000102 ; SDRAMC_CFR1 [FLASH_SAMV71] CHIP = ATSAM ; flash chip FILE = "test256k.bin", 0x400000 ; file to program [SERIAL] BAUD = 115200 STOP_BITS = 1 PARITY = NONE TCP_PORT = 0 ; 2023 [TELNET] PROMPT = "samv71xult> " BACKSPACE = 127 ; comment out for autodetect [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 25 ; beeper volume [ACTIONS] ;AUTORUN = 1 ; executed on every target connect 1 = samba_on 2 = samba_off ;-------------------------------------------------------------------------- ; #10: Memory Remap ;-------------------------------------------------------------------------- [remap] memory w32 0xFFFFFF00 0x00000001 ; memory mapping (intsram @ addr(0)) ;-------------------------------------------------------------------------- ; #14: Samba-Mode On ;-------------------------------------------------------------------------- [samba_on] reset flash erase mem write32 0x400E0C04 0x5A00020D reset ;-------------------------------------------------------------------------- ; #15: Samba-Mode Off ;-------------------------------------------------------------------------- [samba_off] reset flash erase mem write32 0x400E0C04 0x5A00020B reset ; set EEFC : Flash Command Register: 0x400E0C04 write only ; Command = 0x0B = Set GPNVM bit = lower 8bit ; set bit1 -> boot from flash, 0 = ROM ; high arg byte is 0x5A - fixed Key