;-------------------------------------------------------------------------- ; ; ; PEEDI sample target configuration file ; ; Ronetix ; ; Supported devices : LPC4337 ; Board : LPC433x-Xplorer ; ; Revision : 1.0 ; ; Date : January 16, 2015 ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. These licenses must be filled before using this file. ; The [LICENSE] section may contain license keys for one or more PEEDIs. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2010, 1111-1111-1111-1 ; KEY = XXXXX, 2222-2222-2222-2 ; ; The [LICENSE] section may point to an external file which contains ; license keys for one or more PEEDIs. The external file must include ; the text [LICENSE] followed by all keys. ; ; Example: ; [LICENSE] ; FILE = tftp://192.168.3.1/license.txt ; or ; FILE=eep:license.txt ; or ; FILE = ftp://user:password@192.168.3.1/license.txt ; ; ; PEEDI is shipped with license keys stored in "eep:license.txt" and ; printed on a label on the bottom side of PEEDI. ; [LICENSE] FILE = eep://license.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote ; gdb remote REMOTE_PORT = 2000 ; TCP/IP port FLASH0 = FLASH_LPC_A ; FLASH section to be used for core 0 ;FLASH1 = FLASH_LPC_B ; FLASH section to be used for core 1 [TARGET] PLATFORM = Cortex-M ; use JTAG for debug ;PLATFORM = CortexM3_SWD ; use SWD for debug [PLATFORM_Cortex-M] JTAG_CHAIN = 4, 4 ; list of TAP controllers in the JTAG chain JTAG_CLOCK = 5000 ; JTAG Clock in [kHz] TRST_TYPE = OPENDRAIN ; type of TRST output: OPENDRAIN or PUSHPULL RESET_TIME = 20 ; length of RESET pulse in ms; 0 means no RESET CORE0 = Cortex-M, 1 CORE0_STARTUP_MODE = RESET ; stop the core immediately after reset CORE0_RESET_MODE = sysresetreq ; software reset: sysresetreq (default) or vectreset CORE0_ENDIAN = LITTLE ; core is little endian CORE0_BREAKMODE = HARD, 0x1A000000, 0x1A080000 ; breakpoint mode CORE0_WORKSPACE = 0x10000000, 0x8000 CORE0_INIT = INIT_LPC4300 CORE0_FLASH0 = FLASH_LPC_A ; Bank A at address 0x1A000000 CORE0_FLASH1 = FLASH_LPC_B ; Bank B at address 0x1B000000 CORE0_FLASH2 = FLASH_SPI CORE0_PATH = "tftp://192.168.3.60" ; default path CORE1 = Cortex-M, 0 CORE1_STARTUP_MODE = RESET ; stop the core immediately after reset CORE1_ENDIAN = LITTLE ; core is little endian ; don't use sysresetreq because it will reset the M4 core too CORE1_RESET_MODE = vectreset ; software reset: sysresetreq (default) or vectreset CORE1_FLASH0 = FLASH_LPC_A ; Bank A at address 0x1A000000 CORE1_FLASH1 = FLASH_LPC_B ; Bank B at address 0x1B000000 CORE1_WORKSPACE = 0x10000000, 0x8000 CORE1_BREAKMODE = HARD, 0x1B000000, 0x1B080000 ; breakpoint mode CORE1_PATH = "tftp://192.168.3.60" ; default path [PLATFORM_CortexM3_SWD] SWD_CLOCK = 100, 4000 ; SWD Clock in [kHz] RESET_TIME = 0 ; length of RESET pulse in ms; 0 means no RESET CORE = Cortex-M ; TAP is Cortex-M CORE_STARTUP_MODE = RESET ; stop the core immediately after reset CORE_RESET_MODE = sysresetreq ; software reset: sysresetreq (default) or vectreset CORE_ENDIAN = LITTLE ; core is little endian CORE_BREAKMODE = HARD, 0x1A000000, 0x1A080000 ; breakpoint mode CORE_WORKSPACE = 0x10000000, 0x8000 CORE_INIT = INIT_LPC4300 ; init section CORE_FLASH0 = FLASH_LPC_A ; Bank A at address 0x1A000000 CORE_FLASH1 = FLASH_LPC_B ; Bank B at address 0x1B000000 CORE_FLASH2 = FLASH_SPI CORE_PATH = "tftp://192.168.3.1" ; default path ;CORE_SWO = DWT, 10000 ;CORE_SWO = 0, 2001 ;CORE_SWO = 1, 10002 ;CORE_SWO = 2, 10003 ;CORE_PROFILING = 0, 0x40000, 0x100000 [INIT_LPC4300] ; Use "run $m0" to start a small dual core example ; lpc4337-multicore.zip [m0] mem load m4_main.bin 0x20008000 set pc 0x20008000 set sp 0x20009000 go ; Bank A at address 0x1A000000 [FLASH_LPC_A] CHIP = LPC4300 ; flash chip BANK = 0 ; Bank A SET_VECTORS_CHECKSUM = YES ; auto set checksum at address 0x1C CPU_CLOCK = 96000 ; CPU clock is 96 MHz FILE = test256k.bin, BIN, 0x1a000000 ; file to program AUTO_ERASE = NO ; erase before program ; Bank B at address 0x1B000000 [FLASH_LPC_B] CHIP = LPC4300 ; flash chip BANK = 1 ; Bank B SET_VECTORS_CHECKSUM = NO ; auto set checksum at address 0x1C CPU_CLOCK = 96000 ; CPU clock is 96 MHz FILE = test512k.bin, BIN, 0x1b000000 ; file to program AUTO_ERASE = NO [FLASH_SPI] CHIP = SPI25_FLASH ; the SPI FLASH chip will be autodetected CPU = LPC_SPIFI SPIFI_BASE = 0x40003000 FILE = "test256k.bin", BIN, 0 [SERIAL] ; serial port configuration BAUD = 115200 STOP_BITS = 1 PARITY = NONE TCP_PORT = 0 [TELNET] PROMPT = "lpc> " ; telnet prompt ;BACKSPACE = 127 ; comment out for autodetect [DISPLAY] VOLUME = 100 ; beeper volume [ACTIONS] ; user defined scripts ;AUTORUN = 2 ; executed on every target connect 1 = erase 2 = prog [erase] ; erase flash flash erase [prog] ; program flash flash prog