;-------------------------------------------------------------------------- ; ; ; PEEDI sample target configuration file ; ; Ronetix GmbH ; ; Supported devices : Freescale LX2160A ; Supported board : LX2160A-RDB ; ; Revision : 1.0 ; ; Date : Nov 20, 2020 ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. These licenses must be filled before using this file. ; The [LICENSE] section may contain license keys for one or more PEEDIs. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2013, 1111-1111-1111-1 ; KEY = XXXXX, 2222-2222-2222-2 ; ; The [LICENSE] section may point to an external file which contains ; license keys for one or more PEEDIs. The external file must include ; the text [LICENSE] followed by all keys. ; ; Example: ; [LICENSE] ; FILE = tftp://192.168.1.1/license.txt ; or ; FILE=eep:license.txt ; or ; FILE = ftp://user:password@192.168.1.1/license.txt ; ; ; PEEDI is shipped with license keys stored in "eep:license.txt" and ; printed on a label on the bottom side of PEEDI. ; [LICENSE] FILE = eep:license.txt [DEBUGGER] PROTOCOL = gdb_remote ; gdb remote REMOTE_PORT = 2000 ; TCP/IP port [TARGET] PLATFORM = Cortex [PLATFORM_Cortex] JTAG_CHAIN = 4 ; list of TAP controllers in the JTAG chain JTAG_CLOCK = 16000 ; JTAG Clock in [kHz] TRST_TYPE = PUSHPULL RESET_TIME = 10 RESET_TYPE = LX2160A WAKEUP_TIME = 2000 ; delay after power up TIME_AFTER_RESET = 500 ; delay after RST is released CORE0_VERBOSE_INFO = 1 ; print info if CORE0_DEBUG_ADDR is not defined CORE0_DEBUG_ADDR = 0x81010000, 0x81020000 ; CoreSight Debug component CORE0 = Cortex-ARMv8_AMP, 0, 0x6BA00477 ; TAP is Cortex-A CPU RCW_SRC = 0 ; force to hard-coded options ;CORE_RCW1 = 0x50777738; ;CORE_RCW10 = 0x98777738; ;CORE0_RCW31 = 0x12345678 CORE0_STARTUP_MODE = RESET ; stop the core immediately after reset CORE0_ENDIAN = LITTLE ; core is little endian CORE0_BREAKMODE = SOFT ; breakpoint mode CORE0_INIT = INIT_LX2160 CORE0_WORKSPACE = 0x18020000, 1024*32 CORE0_FLASH0 = FLASH_SPI CORE0_PATH = "tftp://192.168.3.60" CORE0_FILE = "test.bin", BIN, 0x20000000 [INIT_LX2160] ; print RCW_SRC[3:0] taken from PORSR1 - POR status register tcl "set x [mrw 0x1e00000]; set x [>> $x 23]; puts RCW_SRC; puth $x" ;mem read 0x01E00000 ; PORSR1 - POR status register mem read 0x01E00100 32 ; show CWSRC1 .. RCW31 mem write 0x02200000 0 ; TZPCR0SIZE - set secure size to 0 mem read 0x01FC8070 ; show MEMORY_INITIALIZATION_STATUS, should be 0x3 [FLASH_SPI] CHIP = SPI25_FLASH CPU = NXP_FSPI_LX2160 ; flash chip ACCESS_METHOD = AGENT ; use agent programming AUTO_ERASE = NO ; erase before program FILE = test32k.bin 0x3000000 ; file to program [SERIAL] [TELNET] PROMPT = "lx2160> " ; telnet prompt ;BACKSPACE = 127 ; comment out for autodetect [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 25 ; beeper volume [ACTIONS] ; user defined scripts ;AUTORUN = 2 ; executed on every target connect 1 = erase 2 = prog [erase] ; erase flash flash erase [prog] ; program flash flash prog