;-------------------------------------------------------------------------- ; ; ; PEEDI sample target configuration file ; ; Ronetix GmbH ; ; Supported devices : Freescale LS1043A - Cortex A53 ; Supported board : LS1043ARDB ; ; Boot settings: ; Pos: 1234-5678 1234-5678 1234-5678 ; boot from NOR : SW3: 1001-0011, SW4 = 0001-0010, SW5 = 1010-0010 (default) ; boot from SDHC: SW4 = 0010-0000, SW5 = 0010-0010 ; boot from NAND: SW4 = 1000-0011, SW5 = 0010-0010 ; ; Please make sure SERDES REF CLK is set to 100 MHz (SW3[4] = 0) ; Set rcw_src to the hard-coded RCW option matching the board's DIP SW ; regarding SYSCLK and differential/single-ended clock source ; ; Use this when SYSCLK = 66 MHz, single-ended clock source ; RCW_SRC = 0x9A ; ; Use this when SYSCLK = 66 MHz, differential clock source ; RCW_SRC = 0x9B ; Use this when SYSCLK = 100 MHz, single-ended clock source ; RCW_SRC = 0x9E ; Use this when SYSCLK = 100 MHz, differential clock source ; RCW_SRC = 0x9F ; ; SW3: 10100011 ; ; SW3[3] = OFF - route serial console to UART1, RS232 ; SW3[3] = ON - route serial console to mini-USB port ; ; ; Note: ; When RCW_SRC config is set to 8-bit NAND flash (SW4[1:8]+SW5[1]: 1_0000_0110), ; LS1043ARDB's CPLD swaps the CS0 and CS1 for NAND flash and NOR flash. ; After swapped, NAND flash will be using CS0. ; Therefore, "CS0: INIT_NOR" and "CS1: INIT_NAND" register setting section ; in ls1043a.cfg must be updated accordingly: ; "CS1: INIT_NAND" -> "CS0: INIT_NAND" ; "CS0: INIT_NOR" -> "CS1: INIT_NOR" ; ; Besides this, ADDR_BASE value in [FLASH_NAND] must change from 1 to 0. ; ; Revision : 1.1 ; ; Date : July 28, 2022 ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. These licenses must be filled before using this file. ; The [LICENSE] section may contain license keys for one or more PEEDIs. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2013, 1111-1111-1111-1 ; KEY = XXXXX, 2222-2222-2222-2 ; ; The [LICENSE] section may point to an external file which contains ; license keys for one or more PEEDIs. The external file must include ; the text [LICENSE] followed by all keys. ; ; Example: ; [LICENSE] ; FILE = tftp://192.168.1.1/license.txt ; or ; FILE=eep:license.txt ; or ; FILE = ftp://user:password@192.168.1.1/license.txt ; ; ; PEEDI is shipped with license keys stored in "eep:license.txt" and ; printed on a label on the bottom side of PEEDI. ; [LICENSE] FILE = eep:license.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote ; gdb remote REMOTE_PORT = 2000 ; TCP/IP port [TARGET] PLATFORM = Cortex-A ; platform is Cortex-A [PLATFORM_Cortex-A] JTAG_CHAIN = 8,4 ; list of TAP controllers in the JTAG chain JTAG_CLOCK = 10000 ; JTAG Clock in [kHz] TRST_TYPE = PUSHPULL ; type of TRST output: OPENDRAIN or PUSHPULL RESET_TIME = 5 ; length of RESET pulse in ms TIME_AFTER_RESET = 20 WAKEUP_TIME = 20 ; delay after power up CORE0_DEBUG_ADDR = 0x80410000, 0x80420000 ; CoreSight Debug and CrossTrigger components RESET_TYPE = LS1043A RCW_SRC = 0x9F ; override RCW source (use hard coded) CORE0 = LS1000_x64, 1, 0x5BA00477 ; TAP is Cortex-A CPU CORE0_STARTUP_MODE = RESET ; stop the core immediately after reset CORE0_ENDIAN = LITTLE ; core is little endian CORE0_BREAKMODE = SOFT ; breakpoint mode CORE0_INIT = INIT_LS1043A ; init section ;CORE0_INIT = INIT_LINUX ; init section with working U-BOOT CORE0_WORKSPACE = 0x10000000, 0x20000 ; address, lenght in bytes CORE0_FLASH0 = FLASH_NOR CORE0_FLASH1 = FLASH_NAND CORE0_FLASH2 = FLASH_MEM_CARD CORE0_PATH = "tftp://192.168.3.60" CORE0_FILE = "test.bin", BIN, 0x20000000 CORE1 = LS1000_x64, 1, 0x5BA00477 ; TAP is Cortex-A CPU CORE1_DEBUG_ADDR = 0x80510000, 0x80520000 ; CoreSight Debug and CrossTrigger components CORE1_STARTUP_MODE = RESET ; stop the core immediately after reset CORE1_WORKSPACE = 0x10000000, 0x20000 ; address, lenght in bytes CORE1_FLASH0 = FLASH_NOR CORE1_FLASH1 = FLASH_NAND CORE1_FLASH2 = FLASH_MEM_CARD CORE1_PATH = "tftp://192.168.3.60" CORE1_FILE = "test.bin", BIN, 0x20000000 CORE2 = LS1000_x64, 1, 0x5BA00477 ; TAP is Cortex-A CPU CORE2_DEBUG_ADDR = 0x80610000, 0x80620000 CORE2_STARTUP_MODE = RESET ; stop the core immediately after reset CORE3 = LS1000_x64, 1, 0x5BA00477 ; TAP is Cortex-A CPU CORE3_DEBUG_ADDR = 0x80710000, 0x80720000 CORE3_STARTUP_MODE = RESET ; stop the core immediately after reset [INIT_LS1043A] mem write 0x2016002C 0x0E000000 ; set secondary cores to debug mode after release mem write 0x01EE00E4 0x0F000000 ; CCSR_BRR: enable all cores mem write 0x2016001C 0x0E000000 ; clear halt request for the secondary cores ; init CSU_CSL mem write 0x01510004 0xFF00FF00 ; CSU_CSL: NOR Flash mem write 0x01510008 0xFF00FF00 ; CSU_CSL: OCRAM1 mem write 0x0151000C 0xFF00FF00 ; CSU_CSL: OCRAM2 ; CS0: INIT_NOR (values are swapped) mem write 0x0153000C 0x00000000 ; IFC_CSPR0_EXT mem write 0x01530010 0x11010060 ; IFC_CSPR0: 0x60000111, 16-bit NOR mem write 0x015300A0 0x000000F8 ; IFC_AMAS0K:0xF8000000, 128 MB mem write 0x01530130 0x01800001 mem write 0x015301C0 0x01000710 mem write 0x015301C4 0x21210001 mem write 0x015301C8 0x0b180401 mem write 0x015301CC 0x00000000 ; CS1: INIT_NAND (values are swapped) mem write 0x01530018 0x00000000 ; IFC_CSPR1_EXT mem write 0x01530140 0x00001000 ; IFC_CSOR1_EXT mem write 0x015301F0 0x0a07180e ; IFC_FTIM0_CS1_NAND mem write 0x015301F4 0x180e3932 ; IFC_FTIM1_CS1_NAND mem write 0x015301F8 0x1e50e001 ; IFC_FTIM2_CS1_NAND mem write 0x015301FC 0 ; IFC_FTIM3_CS1_NAND mem write 0x0153013C 0x00210885 ; IFC_CSOR1_NAND mem write 0x0153001C 0x8300807e ; IFC_CSPR1: BASE=0x7E80, NAND, Valid mem write 0x015300AC 0x0000FFFF ; IFC_AMASK1: 32MB [INIT_LINUX] break add hard 0x80008620 ; kernel break address got by 'nm vmlinux | grep start_kernel' go wait 20000 stop break del all beep 100 100 [FLASH_NAND] CHIP = NAND_FLASH CPU = LS1043A CMD_BASE = 0x01530000 ; IFC address DATA_BASE = 0x7e800000 ; FCM address ADDR_BASE = 1 ; NAND chip select OOB_INFO = FF FILE = "test2m.bin", 0x0 ERASE_BAD_BLOCKS = NO [FLASH_NOR] CHIP = CFI_FLASH CHIP_COUNT = 1 CHIP_WIDTH = 16 BASE_ADDR = 0x60000000 SWAP_DATA = YES ; data bus is byte swapped ACCESS_METHOD = DIRECT ; program method FILE = "test32k.bin", bin, 0x67fe0000 [FLASH_MEM_CARD] CHIP = CARD CPU = LS1021A SDHC = 1 ; should be 1, do not modify ; eMMC relevant partitions: ; 0 - user data ; 1 - boot 1 ; 2 - boot 2 ; ; 'flash this part' manage the eMMC partitions ; 'flash this part help' - print help ; 'flash info' - show the current partition PARTITION = 0 FILE = "test256k.bin", bin, 2 ; program at block 2 [SERIAL] ; serial port configuration BAUD = 115200 STOP_BITS = 1 PARITY = NONE TCP_PORT = 0 [TELNET] PROMPT = "ls1043a> " ; telnet prompt [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 25 ; beeper volume [ACTIONS] ; user defined scripts ;AUTORUN = 2 ; executed on every target connect 1 = erase 2 = prog [erase] ; erase flash flash erase [prog] ; program flash flash prog