;-------------------------------------------------------------------------- ; ; ; PEEDI sample target configuration file ; ; Ronetix GmbH ; ; Supported devices : AM335x ; Supported board : phyCORE®-AM335x ; BeagleBoard Black ; ; Revision : 1.0 ; ; Date : February 25, 2012 ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. These licenses must be filled before using this file. ; The [LICENSE] section may contain license keys for one or more PEEDIs. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2010, 1111-1111-1111-1 ; KEY = XXXXX, 2222-2222-2222-2 ; ; The [LICENSE] section may point to an external file which contains ; license keys for one or more PEEDIs. The external file must include ; the text [LICENSE] followed by all keys. ; ; Example: ; [LICENSE] ; FILE = tftp://192.168.3.1/license.txt ; or ; FILE=eep:license.txt ; or ; FILE = ftp://user:password@192.168.3.1/license.txt ; ; ; PEEDI is shipped with license keys stored in "eep:license.txt" and ; printed on a label on the bottom side of PEEDI. [LICENSE] FILE=eep:license.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote ; gdb remote REMOTE_PORT = 2000 ; TCP/IP port [TARGET] PLATFORM = Cortex [PLATFORM_Cortex] JTAG_CHAIN = 6, 4 ; list of TAP controllers in the JTAG chain JTAG_CLOCK = 1000, 10000 ; JTAG Clock in [kHz] TRST_TYPE = PUSHPULL ; type of TRST output: OPENDRAIN or PUSHPULL RESET_TIME = 100 ; length of RESET pulse in ms; 0 means no RESET RESET_TYPE = ICEPICK-D, 12, 1 ; enable TAP12, warm reset TIME_AFTER_RESET = 200 CORE0 = Cortex-A, 1, 0xBA01477 CORE0_APSEL = 1 CORE0_DEBUG_ADDR = 0xCB141000 CORE0_STARTUP_MODE = RESET ; stop the core immediately after reset CORE0_ENDIAN = LITTLE ; core is little endian CORE0_BREAKMODE = SOFT ; breakpoint mode CORE0_INIT = INIT_AM335x ; init section with working U-BOOT ;CORE0_INIT = INIT_LINUX ; init section with working U-BOOT ;CORE0_WORKSPACE = 0x402F0400, 0x10000 ; 64 KB internal SRAM CORE0_WORKSPACE = 0x80000000, 0x10000 ; 64 KB external DDR3 ;CORE_VECTOR_CATCH_MASK = 0xFE00FCFF ; catch all vectors ; Default path to be used if only a file name (without the full path) is ; provided to a PEEDI command or for the FILE parameter in the Flash sections ; Examples: ; In a console: ; "flash prog tftp://192.168.3.1/image.elf" ; is equal to ; "flash prog image.elf" ;r ; In a Flash Profile: ; FILE="tftp://192.168.3.1/image.bin", BIN, 0 ; is equal to ; FILE="image.bin", BIN, 0 ; CORE0_PATH = "tftp://192.168.3.1" ;CORE0_PATH = "card://" CORE0_FILE = "test.bin", BIN, 0x20000000 [INIT_LINUX] break add hard 0xC00087A0 ; kernel break address got by 'nm vmlinux | grep start_kernel' go wait 10000 stop break del all beep 100 100 [INIT_AM335x] ; Reset ARM ------------------------------------------------------------- set cpsr 0xDF set cpsr 0x13 ; Sets the Counter Program Status Register to a known state ; Disable Watchdog Timer ------------------------------------------------ mem write 0x44E35048 0x0000AAAA ; mem write 0x44E35048 0x00005555 ; ; Setup PLL ------------------------------------------------------------- mem write 0x44E00458 0x0 ;; MPU PLL Config ------------------------------------------------------- mem write 0x44E00488 0x4 ; CM_CLKMODE_DPLL_MPU, DPLL in bypass mode wait 1 ; Wait for clock to stabilize mem and 0x44E0042C 0x80000 ; MPU_PLL_CONFIG mem or 0x44E0042C 0x1f400 mem or 0x44E0042C 0x17 mem and 0x44E004A8 0xE0 ; CM_DIV_M2_DPLL_MPU mem or 0x44E004A8 0x1 mem write 0x44E00488 0x7 ; CM_CLKMODE_DPLL_MPU wait 1 ;; CORE PLL Config ------------------------------------------------------ mem write 0x44E00490 0x4 ; CM_CLKMODE_DPLL_CORE PLL to bypass wait 1 ; mem and 0x44E00468 0x80000 ; CM_CLKSEL_DPLL_CORE mem or 0x44E00468 0x3E800 mem or 0x44E00468 0x17 mem write 0x44E00480 0xA ; CM_DIV_M4_DPLL_CORE mem write 0x44E00484 0x8 ; CM_DIV_M5_DPLL_CORE mem write 0x44E004D8 0x4 ; CM_DIV_M6_DPLL_CORE mem write 0x44E00490 0x7 ; CM_CLKMODE_DPLL_CORE wait 10 ; ;; DDR PLL Config --------------------------------------------------------- mem write 0x44E00494 0x00000004 ; CM_CLKMODE_DPLL_DDR wait 1; mem write 0x44E00440 0x80000 ; CM_CLKSEL_DPLL_DDR mem or 0x44E00440 0x12F00 ; mem or 0x44E00440 0x17 ; mem or 0x44E004A0 0x1 ; CM_DIV_M2_DPLL_DDR mem write 0x44E00494 0x7 ; CM_CLKMODE_DPLL_DDR wait 1; ; Initiazlization for DDR3 external memory ---------------------------------- ;; EMIF_PRCM_CLK_ENABLE ----------------------------------------------------- mem write 0x44E000D0 0x02 ; CM_PER_EMIF_FW_CLKCTRL mem write 0x44E00028 0x02 ; CM_PER_EMIF_CLKCTR wait 1 ; ;; Enable VTP --------------------------------------------------------------- mem write 0x44E10E0C 0x47 wait 1 ; ;; DDR3 PHY Parameters ------------------------------------------------------ ; Info: CMD0_REG_PHY_CTRL_SLAVE_RATIO_0 ; Info: CMD0_REG_PHY_INVERT_CLKOUT_0 mem write 0x44E1201C 0x80 mem write 0x44E1202C 0x0 mem write 0x44E12050 0x80 mem write 0x44E12060 0x0 mem write 0x44E12084 0x80 mem write 0x44E12094 0x0 ; Info: DATA0_REG_PHY_RD_DQS_SLAVE_RATIO_0 (0x44E120C8) ; Info: DATA0_REG_PHY_WR_DQS_SLAVE_RATIO_0 (0x44E120DC) ; Info: DATA0_REG_PHY_FIFO_WE_SLAVE_RATIO_0 (0x44E12108) ; Info: DATA0_REG_PHY_WR_DATA_SLAVE_RATIO_0 (0x44E12120) mem write 0x44E120C8 0x3B mem write 0x44E120DC 0x3C mem write 0x44E12108 0xA5 mem write 0x44E12120 0x74 mem write 0x44E1216C 0x3B mem write 0x44E12180 0x3C mem write 0x44E121AC 0xA5 mem write 0x44E121C4 0x74 ;; Setting I/O Control Module Registers ----------------------------------- mem write 0x44E11404 0x18B ; DDR_CMD0_IOCTRL mem write 0x44E11408 0x18B ; DDR_CMD1_IOCTRL mem write 0x44E1140C 0x18B ; DDR_CMD2_IOCTRL mem write 0x44E11440 0x18B ; DDR_DATA0_IOCTRL mem write 0x44E11444 0x18B ; DDR_DATA1_IOCTRL ; I/O to work for DDR3 ---------------------------------------------------- mem and 0x44E10E04 0xEFFFFFFF ; DDR_IO_CTRL ; CKE controlled by EMIF/DDR_PHY ------------------------------------------ ; mem write 0x44E10E14 0x00000000 ; VREF_CTRL mem or 0x44E1131C 0x1 ; DDR_CKE_CTRL ; Configure EMIF --------------------------------------------------------- ;; EMIF_DDR_PHY_CTRL ----------------------------------------------------- mem write 0x4C0000E4 0x06 mem write 0x4C0000E8 0x06 mem write 0x4C0000EC 0x06 ;; Trimming -------------------------------------------------------------- mem write 0x4C000018 0x0888A39B ; EMIF TIM_1 mem write 0x4C00001C 0x0888A39B ; EMIF_SDRAM_TIM_1_SHDW_REG mem write 0x4C000020 0x26517FDA ; EMIF TIM_2 mem write 0x4C000024 0x26517FDA ; EMIF_SDRAM_TIM_2_SHDW_REG mem write 0x4C000028 0x501F84EF ; EMIF TIM_3 mem write 0x4C00002C 0x501F84EF ; EMIF_SDRAM_TIM_3_SHDW_REG mem write 0x4C000010 0x0000093B ; EMIF SDRAM REFRESH mem write 0x4C000014 0x0000093B ; EMIF_SDRAM_REF_CTRL_SHDW_REG mem write 0x4C0000C8 0x50074BE4 ; EMIF_ZQ_CONFIG_REG mem write 0x4C000008 0x61C04BB2 ; EMIF SDRAM CONFIG wait 1; [SERIAL] ; serial port configuration BAUD = 115200 STOP_BITS = 1 PARITY = NONE TCP_PORT = 0 [TELNET] PROMPT = "AM335x> " ; telnet prompt ;BACKSPACE = 127 ; comment out for autodetect [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 25 ; beeper volume [ACTIONS] ; user defined scripts ;AUTORUN = 2 ; executed on every target connect 1 = erase 2 = prog [erase] ; erase flash flash erase [prog] ; program flash flash prog