;-------------------------------------------------------------------------- ; ; ; PEEDI sample target configuration file ; ; Ronetix ; ; Supported devices : FreeScale MCF5206 ; Boards : SBC5206 evaluation board ; MCF5206 custom board (c~tec, A.K.) ; ; Revision : 1.3 ; ; Date : April 12, 2010 ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. These licenses must be filled before using this file. ; The [LICENSE] section may contain license keys for one or more PEEDIs. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2010, 1111-1111-1111-1 ; KEY = XXXXX, 2222-2222-2222-2 ; ; The [LICENSE] section may point to an external file which contains ; license keys for one or more PEEDIs. The external file must include ; the text [LICENSE] followed by all keys. ; ; Example: ; [LICENSE] ; FILE = tftp://192.168.3.1/license.txt ; or ; FILE=eep:license.txt ; or ; FILE = ftp://user:password@192.168.3.1/license.txt ; ; ; PEEDI is shipped with license keys stored in "eep:license.txt" and ; printed on a label on the bottom side of PEEDI. ; [LICENSE] FILE=eep:license.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote ; gdb remote REMOTE_PORT = 2000 ; TCP/IP port [TARGET] PLATFORM = COLDFIRE ; platform is ColdFire [PLATFORM_COLDFIRE] BDM_CLOCK = adaptive_8 ; BDM Clock is CLKOUT/8 RESET_TIME = 20 ; lenght of RESET pulse in ms; 0 means no RESET CORE = MCF5206 ; CPU is Coldfire V2 CORE_STARTUP_MODE = reset CORE_BREAKMODE = soft ; soft - software breakpiont ; hard - use hardware breakpoints instead of software CORE_INIT = INIT_COLDFIRE ; init section CORE_FLASH0 = FLASH_AM29F080B CORE_FLASH1 = FLASH_AM29F010 ; NOTE - address 0x0 can not be used for workspace CORE_WORKSPACE = 0x10, 1024*64 ; DRAM 64 KB CORE_FILE = "myfile.bin", BIN, 0x20000000 ; default file CORE_PATH = "tftp://192.168.3.60" ; default path [INIT_COLDFIRE] ; Init SIM Module set MBAR 0x10000001 ; MBAR: SIM registers at 0x10000000 set RAMBAR 0x20000001 ; SRAMBAR: Internal SRAM 512 bytes at 0x20000000 mem write8 0x10000003 0x80 ; SIMR: enable bus monitor while freezed mem write8 0x10000041 0x04 ; SYPCR: enable bus monitor (1024 cycles) mem write8 0x100000CB 0x00 ; PAR: Pin Assignment Register PST/DDATA not needed by BDI mem write8 0x10000014 0x85 ; ICR1: mem write8 0x10000015 0x8B ; ICR2: mem write8 0x10000016 0x8E ; ICR3: mem write8 0x10000017 0x92 ; ICR4: mem write8 0x10000018 0x95 ; ICR5: mem write8 0x10000019 0x98 ; IRC6: mem write8 0x1000001A 0x9F ; ICR7: mem write8 0x1000001B 0x1E ; ICR8: SWT mem write8 0x1000001C 0x97 ; ICR9: Timer 1 mem write8 0x1000001D 0x96 ; ICR10: Timer 2 mem write8 0x1000001E 0x8C ; ICR11: MBUS mem write8 0x1000001F 0x8E ; ICR12: UART 1 mem write8 0x10000020 0x8D ; ICR13: UART 2 ; Init DRAM controller mem write16 0x10000046 0x0018 ; DCRR mem write16 0x1000004A 0x0000 ; DCTR mem write16 0x1000004C 0x0000 ; DCAR0 mem write 0x10000050 0x000E0000 ; DCMR0 mem write8 0x10000057 0x07 ; DCCR0 mem write16 0x10000058 0x0000 ; DCAR1 mem write 0x1000005C 0x00000000 ; DCMR1 mem write8 0x10000063 0x00 ; DCCR1 ; Init Chip-Select Module mem write16 0x10000064 0xFFE0 ; CSAR0 ; base address 0xFFE00000 ; CS0 - SBC5206 with 16-bit NOR Flash ; mem write 0x10000068 0x00030000 ; CSMR0 ; 256 KB size ; mem write16 0x1000006E 0x1D83 ; CSCR0 ; 16-bit NOR Flash, 7 wait states ; CS0 - custom board (c~tec, A.K.) with 8-bit NOR Flash mem write 0x10000068 0x000F0000 ; CSMR0 ; 1 MB size mem write16 0x1000006E 0x0D43 ; CSCR0 ; 8-bit NOR Flash ; CS1 mem write16 0x10000070 0xFFFF ; CSAR1 mem write 0x10000074 0x0000001E ; CSMR1 mem write16 0x1000007A 0x0043 ; CSCR1 mem write16 0x1000007C 0x3000 ; CSAR2 mem write 0x10000080 0x00000014 ; CSMR2 mem write16 0x10000086 0x0043 ; CSCR2 mem write16 0x10000088 0x4000 ; CSAR3 mem write 0x1000008C 0x000F0000 ; CSMR3 ; SBC5206 with 16-bit NOR Flash [FLASH_AM29F010] CHIP = AM29F010 ; flash chip ACCESS_METHOD = AGENT ; program method CHECK_ID = YES ; check chip ID CHIP_WIDTH = 8 ; chip is in 16 bit configuration CHIP_COUNT = 2 ; one chip is used BASE_ADDR = 0xFFE00000 ; chip is mapped at 0xFFE00000 FILE = "test256k.bin" bin 0xFFE00000 AUTO_ERASE = NO ; erase before program AUTO_LOCK = NO ; lock after program ; custom board (c~tec, A.K.) with 8-bit NOR Flash [FLASH_AM29F080B] CHIP = AM29F080B ; flash chip ACCESS_METHOD = AGENT ; program method CHECK_ID = YES ; check chip ID CHIP_WIDTH = 8 ; chip is in 16 bit configuration CHIP_COUNT = 1 ; one chip is used BASE_ADDR = 0xFFE00000 ; chip is mapped at 0xFFE00000 FILE = "test256k.bin" bin 0xFFE00000 AUTO_ERASE = NO ; erase before program AUTO_LOCK = NO ; lock after program [SERIAL] ; serial port configuration BAUD = 115200 STOP_BITS = 1 PARITY = NONE TCP_PORT = 0 ; enable CLI over RS232 ;TCP_PORT = 2023 ; enable serial over TCP/IP [TELNET] PROMPT = "MCF5206> " ; telnet prompt ;BACKSPACE = 127 ; comment out for autodetect [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 25 ; zummer volume [ACTIONS] ; user defined scripts ;AUTORUN = 2 ; executed on every target connect 1 = erase 2 = prog 3 = dump_ram 4 = dump_flash [erase] ; erase flash flash erase [prog] ; program flash flash prog