;-------------------------------------------------------------------------- ; ; ; PEEDI sample target configuration file ; ; Ronetix ; ; Supported devices : TI DaVinci TMS320DM355 (ARM926E + DSP) ; Board : DM355 EVM ; NAND Flash : MT29F16G08QAA, 2KB page, 128 pages/block, 256KB block ; ; Revision : 1.2 ; ; Date : May 12, 2010 ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. These licenses must be filled before using this file. ; The [LICENSE] section may contain license keys for one or more PEEDIs. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2010, 1111-1111-1111-1 ; KEY = XXXXX, 2222-2222-2222-2 ; ; The [LICENSE] section may point to an external file which contains ; license keys for one or more PEEDIs. The external file must include ; the text [LICENSE] followed by all keys. ; ; Example: ; [LICENSE] ; FILE = tftp://192.168.3.1/license.txt ; or ; FILE=eep:license.txt ; or ; FILE = ftp://user:password@192.168.3.1/license.txt ; ; ; PEEDI is shipped with license keys stored in "eep:license.txt" and ; printed on a label on the bottom side of PEEDI. ; [LICENSE] FILE=eep:license.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote ; gdb remote REMOTE_PORT = 2000 ; TCP/IP port [TARGET] PLATFORM = ARM [PLATFORM_ARM] ; list of IR lenght of all TAP controller in JTAG chain JTAG_CHAIN = 6, 4 ; EMU0=EMU1=HI (1), IcePick (IRLen 4) - ARM (IRLen 4) ; JTAG_CHAIN = 6, 4, 4 ; EMU0=EMU1=LOW (0), IcePick (IRLen 4) - ARM (IRLen 4) - ETB (IRLen 6) TRST_TYPE = PUSHPULL ; type of TRST output: OPENDRAIN or PUSHPULL WAKEUP_TIME = 300 ; time between releasing the reset and starting the jtag communication RESET_TIME = 20 ; lenght of RESET pulse in ms; 0 means no RESET TIME_AFTER_RESET = 300 RESET_TYPE = ICEPICK-C, 0, 1 CORE0 = ARM926E, 1 ; TAP 1 is DaVinci ARM926E CPU CORE0_STARTUP_MODE = RESET ; startup mode after reset: ; if RESET than no code is executed after reset ; if STOP,XX then the target executes code for XX period in ms. ; if RUN then the target executes code until stopped by the telnet "halt" command CORE0_BREAKMODE = soft ; default breakpoint mode for the debugger: ; soft - use software breakpoints ; hard - use hardware breakpoints JTAG_CLOCK = 100, 20000 ; JTAG Clock in [kHz] - 100kHz jtag clock for init operations and 20MHz for normal work ;CORE0_INIT = INIT_DAVINCI ; init section for DaVinci CPU CORE0_FLASH0 = NAND_UBL CORE0_FLASH1 = NAND_UBOOT CORE0_FLASH2 = NAND_KERNEL CORE0_FLASH3 = NAND_ROOTFS CORE0_FLASH4 = NAND_ROOTFS2 CORE0_ENDIAN = little CORE0_VECTOR_CATCH_MASK = 0 ; 0x18 ; worksapce in SRAM ;CORE0_WORKSPACE_ADDR = 0x2000 ;CORE0_WORKSPACE_LEN = 0x2000 ; length of workspace in bytes ; workspace in DDR2 CORE0_WORKSPACE_ADDR =0x80000000 CORE0_WORKSPACE_LEN =0x18000 ; length of workspace in bytes CORE0_PATH = "ftp://user:password@192.168.3.1" CORE0_FILE = "test.bin", BIN, 0x80000000 ;------------------------------------- ; init for TMS320DM350 ;------------------------------------- [INIT_DAVINCI] set CPSR 0x400000D3 ; Set to supervisor mode, disable IRQ/FIQ ; Disable ARM interrupts mem wr 0x01c48020 4 mem wr 0x01c48024 0 mem wr 0x01c48018 0 mem wr 0x01c4801c 0 mem wr 0x01c48000 0xffffffff mem wr 0x01c48004 0xffffffff mem wr 0x01c48008 0xffffffff mem wr 0x01c4800c 0xffffffff wait 200 ; Setup Pin Mux mem wr 0x01C40000 0x00007F55 ; All Video Inputs mem wr 0x01C40004 0x00145555 ; All Video Outputs mem wr 0x01C40008 0x00000004 ; EMIFA mem wr 0x01C4000C 0x1BFF55FF ; SPI0, SPI1, UART1, I2C, SD0, SD1, McBSP0, CLKOUTs mem wr 0x01C40010 0x00000000 ; MMC/SD0 instead of MS, SPI0 ; Setup PLL1 ; Configure ARM at 216MHz mem and 0x01c40900 0xFFFFFEFF ; Onchip Oscillator mem and 0x01c40900 0xFFFFFFDF ; Clear PLLENSRC mem and 0x01c40900 0xFFFFFFFE ; Set PLL in bypass wait 150 mem or 0x01c40900 0x0008 ; Put PLL in reset mem or 0x01c40900 0x0010 ; Disable PLL mem and 0x01c40900 0xFFFFFFFD ; Power up PLL mem and 0x01c40900 0xFFFFFFEF ; Enable PLL wait 150 ; Wait for PLL to stabilize mem wr 0x01c40910 143 ; PLL1 24 * (143 + 1) / (7 + 1) = 432MHz mem or 0x01c40918 0x8000 ; SYSCLK1 = 432MHz / 2 = 216MHz (ARM) mem or 0x01c4091c 0x8000 ; SYSCLK2 = 432MHz / 4 = 108MHz (Peripherals) mem wr 0x01c40920 0x800F ; SYSCLK3 = 432MHz / 16 = 27MHz (VENC) mem wr 0x01c40960 0x8003 ; SYSCLK4 = 432MHz / 4 = 108MHz (VPSS) wait 100 mem and 0x01c40038 0xFFFFFFD ; Enable high frequency operation mem or 0x01c40938 0x0001 ; Set GOSET wait 1000 mem and 0x01c40900 0xFFFFFFF7 ; Take PLL out of reset wait 1000 mem wr 0x01c40900 0x0001 ; Enable PLL ; Setup PLL2 ; Confogire DDR at 171MHz mem and 0x01c40d00 0xFFFFFEFF ; Onchip Oscillator mem and 0x01c40d00 0xFFFFFFDF ; Clear PLLENSRC mem and 0x01c40d00 0xFFFFFFFE ; Set PLL in bypass wait 150 mem or 0x01c40d00 0x0008 ; Put PLL in reset mem or 0x01c40d00 0x0010 ; Disable PLL mem and 0x01c40d00 0xFFFFFFFD ; Power up PLL mem and 0x01c40d00 0xFFFFFFEF ; Enable PLL wait 150 ; Wait for PLL to stabilize mem wr 0x01c40d10 113 ; PLL2 24 * (113 + 1) / (7+1) = 342MHz mem or 0x01c40d18 0x8000 ; SYSCLK1 = 342MHz / 2 = 171MHz (DDR2) mem or 0x01c40d38 0x0001 ; Set GOSET wait 1000 mem and 0x01c40d00 0xFFFFFFF7 ; Take PLL out of reset wait 1000 mem or 0x01c40d00 0x0001 ; Enable PLL clock normal ; remove this when INIT used for multicore ; Configure DDR2 controller ; Turn on DDR2 PHY in PSC mem and 0x01c40070 0xFFFFDF3F ; Clear bit CLRZ & PWRDN & LOCK bit(bit 13/6/7) mem or 0x01c40070 0x00002000 ; Set bit CLRZ (bit 13) wait 100 mem or 0x01c40070 0x00004000; ; Set bit VTP_IO_READY(bit 14) mem or 0x01c40070 0x00000180; ; Set bit LOCK(bit 7) and PWRSAVE (bit 8) mem or 0x01c40070 0x00000040; ; Powerdown VTP as it is locked (bit 6) ; Disable and then re-enable DDR PSC domain wait 100 ; Step 1 - Wait for PTSTAT.GOSTAT to clear mem and 4*13+0x01C41A00 0xFFFFFFE0 ; Step 2 - Set MDCTLx.NEXT to new state mem or 4*13+0x01C41A00 1 mem or 0x01c41120 1 ; Step 3 - Start power transition ( set PTCMD.GO to 1 ) wait 100 ; Step 4 - Wait for PTSTAT.GOSTAT to clear mem and 4*13+0x01C41A00 0xFFFFFFE0 ; Step 2 - Set MDCTLx.NEXT to new state mem or 4*13+0x01C41A00 3 mem or 0x01C41120 1 ; Step 3 - Start power transition ( set PTCMD.GO to 1 ) wait 100 ; Step 4 - Wait for PTSTAT.GOSTAT to clear ; DDR2 controller initialization mem wr 0x200000E4 0x51006494; ; External DQS gating enabled mem wr 0x2000000C 0x00000535; ; Program SDRAM Refresh Control Register mem wr 0x20000020 0x000000FE; ; VBUSM Burst Priority Register, pr_old_count = 0xFE mem wr 0x20000008 0x0000C632; ; Program SDRAM Bank Config Register mem wr 0x20000010 0x2A923249; ; Program SDRAM Timing Control Register1 mem wr 0x20000014 0x3C17C763; ; Program SDRAM Timing Control Register2 mem wr 0x20000008 0x00004632; ; Program SDRAM Bank Config Register ; Setup AEMIF (CE0 and CE1) ; EMIF configuration for J7 in NAND mode ; Use extended wait cycles to keep CE low during NAND access mem wr 0x01e10004 0xff ; Setup CE0 - 8-bit NAND, 9.26ns/cycle mem wr 0x01e10010 0x40400204; ; Setup=0, Strobe=4, Hold=0, TA=1, 8-bit mem or 0x01e10060 1; ; Setup CE1 - 8-bit NAND, 9.26ns/cycle mem wr 0x01e10014 0x40400204 ; Setup=0, Strobe=4, Hold=0, TA=1, 8-bit mem and 0x01e10060 0xFFFFFFFD set pc 0 ; When the RBL (Rom Boot Loader) starts, it looks for the UBL descriptor ; at page 0 from block 1. If a valid UBL is not found here, ; as determined by reading a proper UBL signature, the next block is ; searched. Searching continues for up to 24 blocks. The format of ; the descriptor is: ; Offset in the page: ; [0] 0x00 - magic word 0xA1ACEDxx ; [1] 0x04 - entry point ; [2] 0x08 - the number of pages the UBL occupies ; [3] 0x0C - start block, starting block in NAND where the UBL can be found ; [4] 0x10 - start page, the starting page within the starting block where the UBL can be found ; [5] 0x14 - load address, the application load address ; ; Note: The RBL doesn't recognize correctly the new NAND Flash devices with extended ID, but ; PEEDI has a built-in workarround ;------------------------------------------------------------------------------ [NAND_UBL] CPU = TMS320DM355 CHIP = NAND_FLASH DATA_BASE = 0x02000000 ; data CMD_BASE = 0x02000010 ; commands (CLE) ADDR_BASE = 0x0200000A ; addreses (ALE) ; Program UBL at page 64 if the NAND Flash has 64 pages per block and 2KB page: 64*2048 ;FILE = "card:ubl.bin", BIN, 2048*64 ;FILE = "ftp://user:password@192.168.3.1/davinci/ubl.bin", BIN, 2048*64 FILE = "tftp://192.168.0.10/davinci/UBL1", BIN, 2048*64 ; list with bad blocks to be marked as bad ;========================================= ;BAD_BLOCKS =10,1633,1881 ; CAUTION!!! ; Enable erasing of bad blocks ; DO NOT Enable this if you don't know what you are doing ; For more information see the AN006 (www.ronetix.at/an006.html) ERASE_BAD_BLOCKS = NO OOB_INFO = DAVINCI_ECC_HW10_512 BURST_MODE = YES ; UBL Signatures and Special Modes ; 0xA1ACED00 - Safe boot mode ; 0xA1ACED11 - DMA boot mode ; 0xA1ACED22 - I Cache boot mode ; 0xA1ACED33 - Fast EMIF boot mode ; 0xA1ACED44 - DMA + I Cache boot mode ; 0xA1ACED55 - DMA + I Cache + Fast EMIF Safe boot mode ; DAVINCI_UBL_DESC_TYPE = 0 DAVINCI_UBL_DESCRIPTOR_MAGIC = 0xA1ACED00 DAVINCI_UBL_DESCRIPTOR_ENTRY_POINT = 0x20 DAVINCI_UBL_DESCRIPTOR_LOAD_ADDR = 0 DAVINCI_UBL_MAX_IMAGE_SIZE = 28*1024 ; When the UBL starts, it looks for an APP descriptor at block 8 and block 9 ; The format of the descriptor table is: ; Offset in the page: ; [0] 0x00 - magic word 0xB1ACED00 ; [1] 0x04 - starting block number where actual application is stored ; [2] 0x08 - Application copy start address in DDR ; [3] 0x0C - Entry point of the main application ; [4] 0x10 - Application size in page numbers ; [5] 0x14 - flag for de-compressing the application ;------------------------------------------------------------------------------ ; U-BOOT at block 8,the first block should be an address table ; U-BOOT should be programmed with hardware ECC ; [NAND_UBOOT] CPU = TMS320DM355 CHIP = NAND_FLASH DATA_BASE = 0x02000000 ; data CMD_BASE = 0x02000010 ; commands (CLE) ADDR_BASE = 0x0200000A ; addreses (ALE) ; NAND Flash with 64 pages (128KB block) ;FILE = "tftp://192.168.0.10/davinci/BOOT", BIN, 2048*64*8 ; NAND Flash with 128 pages (256KB block) FILE = "tftp://192.168.0.10/davinci/BOOT", BIN, 2048*128*8 ; list with bad blocks to be marked as bad ;========================================= ;BAD_BLOCKS=10,1633,1881 ; CAUTION!!! ; Enable erasing of bad blocks ; DO NOT Enable this if you don't know what you are doing ; For more information see the AN006 (www.ronetix.at/an006.html) ERASE_BAD_BLOCKS = NO OOB_INFO = DAVINCI_ECC_HW10_512 BURST_MODE = YES DAVINCI_UBL_DESC_TYPE = 1 DAVINCI_UBL_DESCRIPTOR_MAGIC = 0xB1ACED22 DAVINCI_UBL_DESCRIPTOR_ENTRY_POINT = 0x81080000 DAVINCI_UBL_DESCRIPTOR_LOAD_ADDR = 0x81080000 DAVINCI_UBL_MAX_IMAGE_SIZE = 1024*1024 ; Linux kernel at address 0x400000 ; the kernel should be programmed with hardware ECC ; [NAND_KERNEL] CPU = TMS320DM355 CHIP = NAND_FLASH DATA_BASE = 0x02000000 ; data CMD_BASE = 0x02000010 ; commands (CLE) ADDR_BASE = 0x0200000A ; addreses (ALE) ;FILE = "card:uimage.bin", BIN, 512*512 ;FILE = "ftp://user:password@192.168.3.1/davinci/uImage1", BIN, 0x400000 FILE = "tftp://192.168.0.10/davinci/KERNEL", BIN, 0x400000 AUTO_ERASE = YES ; list with bad blocks to be marked as bad ; ;BAD_BLOCKS = 10,1633,1881 ; CAUTION!!! ; Enable erasing of bad blocks ; DO NOT Enable this if you don't know what you are doing ; For more information see the AN006 (www.ronetix.at/an006.html) ERASE_BAD_BLOCKS = NO OOB_INFO = DAVINCI_ECC_HW10_512 BURST_MODE = YES ; JFFS2 root filesystem, at page 16384 ; the rootfs should be programmed with hardware ECC HW10_512 ; [NAND_ROOTFS] CPU = TMS320DM355 CHIP = NAND_FLASH DATA_BASE = 0x02000000 ; data CMD_BASE = 0x02000010 ; commands (CLE) ADDR_BASE = 0x0200000A ; addreses (ALE) FILE = "tftp://192.168.0.10/davinci/JFFS2", BIN, 512*16384 ;FILE = "ftp://user:password@192.168.3.1/davinci/rootfs.jffs2", BIN, 512*16384 ; list with bad blocks to be marked as bad ;BAD_BLOCKS = 1633,1881 ; CAUTION!!! ; Enable erasing of bad blocks ; DO NOT Enable this if you don't know what you are doing ; For more information see the AN006 (www.ronetix.at/an006.html) ;ERASE_BAD_BLOCKS = NO OOB_INFO = YAFFS BURST_MODE = YES AUTO_ERASE = YES ; JFFS2 root filesystem, at page 16384 ; the rootfs should be programmed with hardware ECC HW10_512 ; [NAND_ROOTFS2] CPU = TMS320DM355 CHIP = NAND_FLASH DATA_BASE = 0x02004000 ; data CMD_BASE = 0x02004010 ; commands (CLE) ADDR_BASE = 0x0200400A ; addreses (ALE) FILE = "tftp://192.168.0.10/davinci/JFFS2", BIN, 512*16384 ;FILE = "ftp://user:password@192.168.3.1/davinci/rootfs.jffs2", BIN, 512*16384 ; list with bad blocks to be marked as bad ;BAD_BLOCKS = 1633,1881 ; CAUTION!!! ; Enable erasing of bad blocks ; DO NOT Enable this if you don't know what you are doing ; For more information see the AN006 (www.ronetix.at/an006.html) ;ERASE_BAD_BLOCKS = NO OOB_INFO = YAFFS BURST_MODE = YES AUTO_ERASE = YES [SERIAL] BAUD = 115200 STOP_BITS = 1 PARITY = NONE TCP_PORT = 0 ; 2023 [TELNET] PROMPT = "dm355> " ; telnet prompt ;BACKSPACE=127 ; comment out for autodetect [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 25 ; beeper volume [ACTIONS] ; user defined scripts ;AUTORUN = 2 ; executed on every target connect 1 = erase 2 = prog [prog] flash set 0 flash erase flash program flash set 1 flash program flash set 2 flash program