;-------------------------------------------------------------------------- ; ; ; PEEDI target configuration file for STR9 microcontroller ; ; Ronetix ; ; Supported devices : STR9 ; ; Revision : 1.5 ; ; Date : May 12, 2010 ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. These licenses must be filled before using this file. ; The [LICENSE] section may contain license keys for one or more PEEDIs. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2010, 1111-1111-1111-1 ; KEY = XXXXX, 2222-2222-2222-2 ; ; The [LICENSE] section may point to an external file which contains ; license keys for one or more PEEDIs. The external file must include ; the text [LICENSE] followed by all keys. ; ; Example: ; [LICENSE] ; FILE = tftp://192.168.3.1/license.txt ; or ; FILE=eep:license.txt ; or ; FILE = ftp://user:password@192.168.3.1/license.txt ; ; ; PEEDI is shipped with license keys stored in "eep:license.txt" and ; printed on a label on the bottom side of PEEDI. ; [LICENSE] FILE=eep:license.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote ; gdb remote REMOTE_PORT = 2000 ; TCP/IP port GDB_READ_INGNORE_TIME = 3000 [TARGET] PLATFORM = ARM ; platform is ARM [PLATFORM_ARM] JTAG_CHAIN = 5, 4, 8 ; list of IR length of all ; TAP controller in JTAG chain JTAG_CLOCK = 10, 4000 ; JTAG Clock in [kHz] - 10kHz ; JTAG clock for init operations and ; 4MHz for normal work TRST_TYPE = PUSHPULL ; type of TRST output: OPENDRAIN ; or PUSHPULL WAKEUP_TIME = 200 ; time between releasing the reset and ; starting the jtag communication RESET_TIME = 20 ; length of RESET pulse in ms; 0 means ; no RESET CORE0 = STR9, 1 ; TAP is ARM966E CPU CORE0_STARTUP_MODE = RESET ; startup mode after reset: ; if RESET than no code is executed after reset ; if STOP,XX then the target executes code for XX period in ms. ; if RUN then the target executes code until stopped by the telnet "halt" command CORE0_BREAK_PATTERN = 0xDFFFDFFF ; software breakpoint pattern CORE0_BREAKMODE = soft ; breakpoint mode: ; soft - use software breakpoints ; hard - use hardware breakpoints CORE0_INIT = INIT_STR9 ; init section for a STR7 board CORE0_FLASH = FLASH_STR9 ; FLASH section parameters CORE0_ENDIAN = LITTLE ; core is little endian CORE0_WORKSPACE = 0x4000000, 0x9000 ; workspace for programmer CORE0_LOCKOUT_RECOVERY = NO ; do not erase device if secured CORE0_FILE = "test.bin", BIN, 0x0 ; default file CORE0_PATH = "tftp://192.168.3.1" ; default path for memory commands [INIT_STR9] mem write 0x5C002004 0x000BC019 ; SCU_PLLCONF: PLL=ENA,P=0x3,N=0xC0,M=0x19 wait 100 mem write 0x5C002000 0x00020000 ; SCU_CLKCNTR: MCLK=PLLC0W ; switch to normal JTAG clock clock normal ; remove this when INIT used for multicore mem write 0x5c00200C 0x00000000 ; SCU_PWRMNG Power Mode = Run mode mem write 0x5C002014 0x0000001B ; SCU_PCGR0 FLI, PQFBC, SRAM, SRAM_ARBITER clk enable mem write 0x5C00201C 0x00001013 ; SCU_PRR0 FLI, PQFBC, SRAM, SRAM_ARBITER, RST_PFQBC_AHB out of reset mem write 0x5C002034 0x00000006 ; SCU_SCR0 WSR_DTCM, WSR_AHB, SRAM_SIZE = 32kB ;mem write 0x54000000 0x3 ; FMI_BBSR, bank0 size 256KB mem write 0x54000000 0x4 ; FMI_BBSR, bank0 size 512KB mem write 0x54000004 0x2 ; bank1 size 64KB mem write 0x5400000C 0x0 ; bank0 base address: 0x00000000 mem write 0x54000010 0x20000 ; boot1 base address: 0x00080000 mem write 0x54000018 0x18 ; enable bank0 and bank1 mem write 0x5C002034 0x018E ; enable 64KB RAM ; mem write 0x5C002034 0x0196 ; enable 96KB RAM set control 0x1F70 ; disable write buffer [FLASH_STR9] CHIP = STR9_256KB ; flash chip, 256 kB ;CHIP = STR9_512KB ; flash chip, 512 kB ACCESS_METHOD = AGENT SECURE_FLASH = NO FILE = "tftp://192.168.3.1/test256k.bin" BIN, 0 ; file to program AUTO_ERASE = YES ; erase before program [SERIAL] ; serial port configuration BAUD = 115200 STOP_BITS = 1 PARITY = NONE TCP_PORT = 0 ; enable CLI over RS232 ;TCP_PORT = 2023 ; enable serial over TCP/IP [TELNET] PROMPT = "str9> " ; telnet prompt ;BACKSPACE = 127 ; comment out for autodetect [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 25 ; beeper volume [ACTIONS] ; user defined scripts ;AUTORUN = 2 ; executed on every target connect 1 = erase 2 = prog 3 = config_secure [erase] ; erase flash flash erase [prog] ; program flash flash prog flash verif [config_secure] ; ISC_ENABLE JTAG reset 1 lsb 0 idle ; reset TAPs JTAG ri 17 lsb 0x1FF0C idle ; IR = ISC_ENABLE JTAG rd 10 lsb 0x3FF ilde ; DR = 2+8 dont care bits echo programming config JTAG ri 17 lsb 0x1FF11 idle ; IR = ISC_ADDRESS_SHIFT JTAG rd 10 lsb 0x50 ilde ; DR = Configuration register JTAG ri 17 lsb 0x1FF20 pause ; IR = ISC_PROGRAM JTAG pud 32 lsb 0x00000000 stop; write 32 bits JTAG st 32 lsb 0x00010000 stop ; write 32 bits JTAG st 2 lsb 0x3 idle ; write 2 bypass bits and wait in pause wait 1000 echo securing device JTAG ri 17 lsb 0x1FF11 idle ; IR = ISC_ADDRESS_SHIFT JTAG rd 10 lsb 0x80 ilde ; DR = Configuration register 0x80+2bits JTAG ri 17 lsb 0x1FF22 idle ; IR = ISC_PROGRAM_SECURITY JTAG rd 2 lsb 0x3 idle ; skip the two bypass bits wait 1000 ; ISC_DISABLE JTAG ri 17 lsb 0x1FF0C idle ; IR = ISC_DISABLE JTAG rd 10 lsb 0x3FF ilde ; DR = 2+8 dont care bits