;-------------------------------------------------------------------------- ; ; ; PEEDI sample target configuration file ; ; Supported devices : Samsung S3C2442 ; Board : custom evaluation board ; ; Revision : 10.0 ; ; Date : 08-01-2007 ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. These licenses must be filled before using this file. ; The [LICENSE] section may contain license keys for one or more PEEDIs. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2010, 1111-1111-1111-1 ; KEY = XXXXX, 2222-2222-2222-2 ; ; The [LICENSE] section may point to an external file which contains ; license keys for one or more PEEDIs. The external file must include ; the text [LICENSE] followed by all keys. ; ; Example: ; [LICENSE] ; FILE = tftp://192.168.3.1/license.txt ; or ; FILE=eep:license.txt ; or ; FILE = ftp://user:password@192.168.3.1/license.txt ; ; ; PEEDI is shipped with license keys stored in "eep:license.txt" and ; printed on a label on the bottom side of PEEDI. ; [LICENSE] FILE=eep:license.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote ; gdb remote REMOTE_PORT = 2000 ; TCP/IP port [TARGET] PLATFORM = ARM [PLATFORM_ARM] JTAG_CHAIN = 4 ; list of IR lenght of all TAP controller in JTAG chain JTAG_CLOCK = 20, 20000 ; JTAG Clock in [kHz] - 10kHz jtag clock for init operations and 20MHz for normal work ;JTAG_CLOCK = adaptive ; JTAG Clock Adaptive TRST_TYPE = PUSHPULL ; type of TRST output: OPENDRAIN or PUSHPULL RESET_TIME = 20 ; length of RESET pulse in ms; 0 means no RESET TIME_AFTER_RESET = 20 ; time between releasing the reset and starting the jtag communication CORE0 = ARM920T ; TAP 0 is ARM920T CORE0_BREAK_PATTERN = 0xDFFFDFFF ; software breakpoint pattern CORE0_BREAKMODE = soft ; breakpoint mode: ; soft - software breakpiont ; hard - use hardware breakpoints instead of software CORE0_INIT = INIT_S3C2442 ; init section for board CORE0_STARTUP_MODE = RESET ; if RESET than no code is executed after reset ; if STOP then PEEDI lets the target execute code for 300 ms. ; if RUN then the target excutes code until stopped by the telnet "halt" command CORE0_FLASH = NAND_K9F1G08 CORE0_ENDIAN = little CORE0_WORKSPACE_ADDR= 0x30010000 ; start address of workspace for flash programmer CORE0_WORKSPACE_LEN = 0x10000 ; length of workspace in bytes (min. 1536(0x600) bytes) CORE0_FILE = "myfile.bin", BIN, 0x30010000 ; default file CORE0_PATH = "tftp://192.168.3.1" ; default path ;------------------------------------------------------------------- ; CORE_VECTOR_CATCH_MASK ; ---------------------- ; ARM9 only: If one of the bits is set HIGH and the corresponding exception occurs, the ; processor enters debug state as if a breakpoint has been set on an instruction fetch ; from the relevant exception vector. ; ; bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ;---------------------------------------------------------- ;| fiq | irq | res |d_abort| p_abort| swi | undef | reset | ;---------------------------------------------------------- CORE_VECTOR_CATCH_MASK = 0x00 [INIT_S3C2442] mem write 0x53000000 0x0 ; disable watchdog ;/////////////////////////////////////////////////////// ; case 1 - clock = 16.9344MHz ;mem write 0x4c000014 0x1 ; set clkdiv = 1:1:2 (95.96MHz) mem write 0x4c000014 0x7 ; set clkdiv : 1:3:6 (296.35MHz) mem write 0x4c000008 0x3c041 ; UPLL PMS 95.96MHz mem write 0x4c000004 0x61012 ; MPLL PMS 296.35MHz ;/////////////////////////////////////////////////////// ;SDRAM Initialization = 2M x32 x 4Banks 8K refresh cycle ;/////////////////////////////////////////////////////// ; bank 0~7 configure mem write 0x48000000 0x22000000 ; set x32 mem write 0x48000004 0x700 ; ((0<<13)+(0<<11)+(7<<8)+(0<<6)+(0<<4)+(0<<2)+0) mem write 0x48000008 0x700 ; ((0<<13)+(0<<11)+(7<<8)+(0<<6)+(0<<4)+(0<<2)+0) mem write 0x4800000c 0x700 ; ((0<<13)+(0<<11)+(7<<8)+(0<<6)+(0<<4)+(0<<2)+0) mem write 0x48000010 0x700 ; ((0<<13)+(0<<11)+(7<<8)+(0<<6)+(0<<4)+(0<<2)+0) mem write 0x48000014 0x700 ; ((0<<13)+(0<<11)+(7<<8)+(0<<6)+(0<<4)+(0<<2)+0) mem write 0x48000018 0x700 ; ((0<<13)+(0<<11)+(7<<8)+(0<<6)+(0<<4)+(0<<2)+0) ; [Bank6/7: SDRAM, Trcd:2clock, CA:8-bit] ; msp ;mem write 0x4800001c 0x18000 ; ((3<<15)|(0<<2)|0) ;mem write 0x48000020 0x18000 ; ((3<<15)|(0<<2)|0) ; s3c2440A only mem write 0x4800001c 0x18000 ; ((3<<15)|(0<<2)|1) mem write 0x48000020 0x18001 ; ((3<<15)|(0<<2)|0) ; [SDRAM refresh enable, Trp=2clk, Trc=Trp+Tsrc=2+5=7clk, Refresh:1278=0x4fe(98MHz)] mem write 0x48000024 0x8404fe ; ((1<<23)+(0<<22)+(0<<20-Trp)+(1<<18-Tsrc)+1278) ; [SCKE_EN enable, SCLK_EN enable, Bank6/7 memory map: 64MB/64MB] mem write 0x48000028 0x11 ; (0x1+(1<<5)+(1<<4)) ; [Bank6/7 CL: 3-clocks] mem write 0x4800002c 0x30 mem write 0x48000030 0x30 wait 50 ; setup GPIOs mem write 0x56000000 0x003FFFFF ; GPACON (configure nFCE, nRSTOUT, nFRE, nFWE, ALE, CLE, nCS5 pins as INPUTS) mem write 0x56000004 0x10000 ; GPADAT (set nCS5/GPA) mem write 0x56000000 0x003EFFFF ; GPACON (configure nFCE, nRSTOUT, nFRE, nFWE, ALE, CLE pins as INPUTS) ; INIT NAND Controller on S3C2442 mem write 0x4E000000 0x0600 ; NFCONF = (6 << 8) --> TWRPH0 3-clk mem write 0x4E000004 0x0013 ; NFCONT = (1 << 4) | (1 << 1) | (1 << 0) --> INIT_ECC + nFCE + MODE mem write 0x4E000020 0x0000 ; NFSTAT = 0 ; RESET NAND Controller on S3C2442 mem write 0x4E000004 0x11 ; NFCONT &= ~(1 << 1) nFCE LOW / CS_ASSERT (MODE remains "1") mem write 0x4E000020 0x04 ; NFSTAT |= (1 << 2) CLEAR R/B mem write 0x4E000008 0xFF ; NFCMD = 0xFF - RESET Issue a RESET Command ; Wait to NFSTAT Read/Busy clear wait 200 mem write 0x4E000004 0x13 ; NFCONT |= (1 << 1) nFCE HIGH / CS_RELEASE (MODE remains "1") wait 100 [NAND_K9F1G08] CHIP = NAND_FLASH DATA_BASE = 0x4E000010 ; NFDATA CMD_BASE = 0x4E000008 ; NFCMD ADDR_BASE = 0x4E00000C ; NFADDR ; address and value for asserting the Nand Flash Chip select ; [addr] = value CS_ASSERT = 0x4E000004, 0x11 ; address and value for releasing the Nand Flash Chip select ; [addr] = value CS_RELEASE = 0x4E000004, 0x13 BURST_MODE = NO FILE="test.bin", 0x0 ; list with bad blocks to be marked as bad ;========================================= ;BAD_BLOCKS= ; CAUTION!!! ; Enable erasing of bad blocks ; DO NOT Enable this if you don't know what you are doing ; For more information see the AN006 (www.ronetix.at/an006.html) ERASE_BAD_BLOCKS=NO OOB_INFO = JFFS2 ; how to deal with the OOB (spare) info ; RAW - program 528/2112 bytes from file ; JFFS2 - program 512/2048 bytes from file and add ECC bytes ; FF - program 512/2048 bytes from file, set spare info to 0xFF ;AUTO_ERASE=NO [SERIAL] BAUD=115200 STOP_BITS=1 PARITY=NONE TCP_PORT = 0 ; enable CLI over RS232 ;TCP_PORT = 2023 ; enable serial over TCP/IP [TELNET] PROMPT = "s3c2442> " ; telnet prompt ;BACKSPACE=127 ; comment out for autodetect [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 25 ; beeper volume [ACTIONS] ; user defined scripts ;AUTORUN = 2 ; executed on every target connect 1 = erase 2 = prog [erase] ; erase flash flash erase [prog] ; program flash flash prog