;-------------------------------------------------------------------------- ; ; ; PEEDI sample target configuration file ; ; Supported devices : Samsung S3C2440 ; Board : custom evaluation board ; ; Revision : 10.0 ; ; Date : 07-05-2008 ; ; NAND base addr = 0x0000_0000 ; SDRAM base addr = 0x3000_0000 ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. These licenses must be filled before using this file. ; The [LICENSE] section may contain license keys for one or more PEEDIs. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2010, 1111-1111-1111-1 ; KEY = XXXXX, 2222-2222-2222-2 ; ; The [LICENSE] section may point to an external file which contains ; license keys for one or more PEEDIs. The external file must include ; the text [LICENSE] followed by all keys. ; ; Example: ; [LICENSE] ; FILE = tftp://192.168.3.1/license.txt ; or ; FILE=eep:license.txt ; or ; FILE = ftp://user:password@192.168.3.1/license.txt ; ; ; PEEDI is shipped with license keys stored in "eep:license.txt" and ; printed on a label on the bottom side of PEEDI. ; [LICENSE] FILE=eep:license.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote ; gdb remote REMOTE_PORT = 2000 ; TCP/IP port [TARGET] PLATFORM = ARM [PLATFORM_ARM] JTAG_CHAIN = 4 ; list of IR lenght of all TAP controller in JTAG chain JTAG_CLOCK = 20, 16000 ; JTAG Clock in [kHz] - 10kHz jtag clock for init operations and 20MHz for normal work TRST_TYPE = PUSHPULL ; type of TRST output: OPENDRAIN or PUSHPULL RESET_TIME = 20 ; length of RESET pulse in ms; 0 means no RESET TIME_AFTER_RESET = 20 ; time between releasing the reset and starting the jtag communication CORE0 = ARM920T ; TAP 0 is ARM920T CORE0_BREAK_PATTERN = 0xDFFFDFFF ; software breakpoint pattern CORE0_BREAKMODE = soft ; breakpoint mode: ; soft - software breakpiont ; hard - use hardware breakpoints instead of software CORE0_INIT = INIT_S3C2440 ; init section for board CORE0_STARTUP_MODE = RESET ; if RESET than no code is executed after reset ; if STOP then PEEDI lets the target execute code for 300 ms. ; if RUN then the target excutes code until stopped by the telnet "halt" command CORE0_FLASH0 = NAND_STEPLDR CORE0_FLASH1 = NAND_EBOOT CORE0_ENDIAN = little CORE0_WORKSPACE_ADDR= 0x30010000 ; start address of workspace for flash programmer CORE0_WORKSPACE_LEN = 0x10000 ; length of workspace in bytes CORE0_FILE = "myfile.bin", BIN, 0x30010000 ; default file CORE0_PATH = "tftp://192.168.3.1" ; default path ;------------------------------------------------------------------- ; CORE_VECTOR_CATCH_MASK ; ---------------------- ; ARM9 only: If one of the bits is set HIGH and the corresponding exception occurs, the ; processor enters debug state as if a breakpoint has been set on an instruction fetch ; from the relevant exception vector. ; ; bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ;---------------------------------------------------------- ;| fiq | irq | res |d_abort| p_abort| swi | undef | reset | ;---------------------------------------------------------- CORE_VECTOR_CATCH_MASK = 0x00 [INIT_S3C2440] mem write 0x53000000 0x00000000 ; WTCON: disable watch dog mem write 0x4A000008 0xFFFFFFFF ; INTMSK mem write 0x4A00001C 0x00007FFF ; INTSUBMSK ; setup PLL mem write 0x4C000014 0x00000007 ; CLKDIVN, 1:3:6 set control 0xc0000078 mem write 0x4C000000 0x00FFFFFF ; PLL lock time counter mem write 0x4C000018 0x00000000 ; CAMDIVN mem write 0x4C000004 0x0003E021 ; MPLLCON, Fin=16MHz, Fout=296MHz wait 100 mem write 0x48000000 0x2211D120 ; BWSCON mem write 0x48000004 0x00000700 ; BANKCON0 mem write 0x48000008 0x00000700 ; BANKCON1 mem write 0x4800000C 0x00000700 ; BANKCON2 mem write 0x48000010 0x00000700 ; BANKCON3 mem write 0x48000014 0x00000700 ; BANKCON4 mem write 0x48000018 0x00000700 ; BANKCON5 mem write 0x4800001C 0x00018009 ; BANKCON6 mem write 0x48000020 0x00018009 ; BANKCON7 mem write 0x48000024 0x00AE0459 ; REFRESH mem write 0x48000028 0x000000B2 ; BANKSIZE mem write 0x4800002C 0x00000020 ; MRSRB6 mem write 0x48000030 0x00000020 ; MRSRB7 wait 100 mem write 0x56000054 0x00000060 ; GPFDAT mem write 0x4E000000 0x00003770 ; NFCONF NAND flash configuration mem write 0x4E000004 0x00000013 ; NFCONT mem write 0x4E000020 0x00000004 ; NFSTAT [NAND_STEPLDR] CHIP = NAND_FLASH DATA_BASE = 0x4E000010 ; NFDATA CMD_BASE = 0x4E000008 ; NFCMD ADDR_BASE = 0x4E00000C ; NFADDR CS_ASSERT = 0x4E000004, 0x0001 CS_RELEASE = 0x4E000004, 0x0003 BURST_MODE = NO FILE = "STEPLDR.nb0", 0x0, bin ERASE_BAD_BLOCKS=NO OOB_INFO = FF ;BAD_BLOCKS= ;AUTO_ERASE=NO [NAND_EBOOT] CHIP = NAND_FLASH DATA_BASE = 0x4E000010 ; NFDATA CMD_BASE = 0x4E000008 ; NFCMD ADDR_BASE = 0x4E00000C ; NFADDR CS_ASSERT = 0x4E000004, 0x0001 CS_RELEASE = 0x4E000004, 0x0003 BURST_MODE = NO FILE = "EBOOT.nb0", 64*2048*2, bin ERASE_BAD_BLOCKS=NO OOB_INFO = FF ;BAD_BLOCKS= ;AUTO_ERASE=NO [SERIAL] BAUD=115200 STOP_BITS=1 PARITY=NONE TCP_PORT=0 [TELNET] PROMPT = "s3c2440> " ; telnet prompt ;BACKSPACE=127 ; comment out for autodetect [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 25 ; beeper volume [ACTIONS] ; user defined scripts ;AUTORUN = 2 ; executed on every target connect 1 = erase 2 = prog [erase] ; erase flash flash erase [prog] ; program flash flash prog