;-------------------------------------------------------------------------- ; ; ; PEEDI sample target configuration file ; ; Ronetix ; ; Supported devices : Freescale iMX27 ; Board : custom board ; ; Revision : 1.0 ; ; Date : Oct 28, 2008 ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. These licenses must be filled before using this file. ; The [LICENSE] section may contain license keys for one or more PEEDIs. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2010, 1111-1111-1111-1 ; KEY = XXXXX, 2222-2222-2222-2 ; ; The [LICENSE] section may point to an external file which contains ; license keys for one or more PEEDIs. The external file must include ; the text [LICENSE] followed by all keys. ; ; Example: ; [LICENSE] ; FILE = tftp://192.168.3.1/license.txt ; or ; FILE=eep:license.txt ; or ; FILE = ftp://user:password@192.168.3.1/license.txt ; ; ; PEEDI is shipped with license keys stored in "eep:license.txt" and ; printed on a label on the bottom side of PEEDI. ; [LICENSE] FILE=eep:license.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote ; gdb remote REMOTE_PORT = 2000 ; TCP/IP port [TARGET] PLATFORM = ARM [PLATFORM_ARM] JTAG_CHAIN = 4, 4 ; list of IR lenghts of all TAP controller in JTAG chain JTAG_CLOCK = 500, 10000 ; JTAG Clock in [kHz] TRST_TYPE = PUSHPULL ; type of TRST output: OPENDRAIN or PUSHPULL RESET_TIME = 20 ; lenght of RESET pulse in ms; 0 means no RESET CORE0 = ARM926E, 0 ; TAP 0 is ARM926E CPU CORE0_STARTUP_MODE = RESET ; startup mode after reset: ; if RESET than no code is executed after reset ; if STOP,XX then the target executes code for XX period in ms. ; if RUN then the target executes code until stopped by the telnet "halt" command CORE0_BREAKMODE = soft ; default breakpoint mode for the debugger: ; soft - use software breakpoints ; hard - use hardware breakpoints CORE_BREAK_PATTERN = 0xDFFFDFFF ; software breakpoint pattern CORE0_INIT = INIT_MX27 ; init section CORE0_FLASH0 = U-BOOT CORE0_FLASH1 = ROOTFS_NAND CORE0_ENDIAN = little CORE0_WORKSPACE_ADDR = 0xA0001000 ; start address of workspace for flash programmer CORE0_WORKSPACE_LEN = 0x10000 ; length of workspace in bytes CORE0_VECTOR_CATCH_MASK = 0xFF CORE0_PATH = "tftp://192.168.3.1" ; default path ;CORE0_PATH = "card://" ; default path CORE0_FILE = "test.bin", BIN, 0xA0000000 ;------------------------------------------------- ; Init for Freescale M9328MX27ADS board (CPU: M9328MX27) ; memory map: ; DDR SDRAM - 0xA0000000 - 128 MB ; Flash - 0xC0000000 - 32 MB ; PSRAM - 0xD6000000 - 16 MB ; ; Caution: ; On some boards pin.1 and pin.2 of the JTAG connector ; privide different voltages. In a such case please disconnect pin.2 ; This is necessary because on the PEEDI's side pin.1 and pin.2 are ; conencted together. ; ;------------------------------------------------- [INIT_MX27] ; AHB-Lite IP Interface mem write 0x10000000 0x20040304 mem write 0x10020000 0x00000000 mem write 0x10000004 0xDFFBFCFB mem write 0x10020004 0xFFFFFFFF ; Set clocks mem and 0x10027000 0xFFFFFFFC mem write 0x10027004 0x00331C23 mem write 0x1002700C 0x040C2403 mem write 0x10027000 0x33FF8107 wait 100 mem write 0x10027818 0x00050F08 mem write 0x10027018 0x130410C3 mem write 0x1002701c 0x09030908 mem write 0x10027028 0x00008307 ; Configure DDR on CSD0 -- initial reset mem write 0xD8001010 0x00000008 ; Configure PSRAM on CS5 mem write 0xd8002050 0x0000dcf6 mem write 0xd8002054 0x444a4541 mem write 0xd8002058 0x44443302 ; Configure 16 bit NorFlash on CS0 mem write 0xd8002000 0x0000CC03 mem write 0xd8002004 0xa0330D01 mem write 0xd8002008 0x00220800 ; Configure CPLD on CS4 mem write 0xd8002040 0x0000DCF6 mem write 0xd8002044 0x444A4541 mem write 0xd8002048 0x44443302 ; Configure DDR on CSD0 -- wait 5000 cycle mem write 0xD8001010 0x00000008 mem write 0x10027828 0x55555555 mem write 0x10027830 0x55555555 mem write 0x10027834 0x55555555 mem write 0x10027838 0x00005005 mem write 0x1002783C 0x15555555 mem write 0xD8001010 0x00000004 mem write 0xD8001004 0x00795729 mem write 0xD8001000 0x92200000 mem read 0xA0000F00 mem write 0xD8001000 0xA2200000 mem read 0xA0000F00 mem read 0xA0000F00 mem write 0xD8001000 0xB2200000 mem read8 0xA0000033 mem read8 0xA1000000 mem write 0xD8001000 0x82228485 [U-BOOT] CHIP = 28F256P30T ; flash chip CHIP = 28F128P30T ; flash chip CHIP = 28F256P30B ; flash chip CHIP = 28F128P30B ; flash chip ACCESS_METHOD = AGENT ; program method auto CHECK_ID = YES ; check chip ID CHIP_WIDTH = 16 ; chip is in 16 bit configuration CHIP_COUNT = 1 ; two chip are used FILE = "u-boot.bin", BIN, 0 ; file to program AUTO_ERASE = YES ; erase before program AUTO_LOCK = NO ; lock after program BASE_ADDR = 0xC0000000 [ROOTFS_NAND] CHIP = NAND_FLASH CPU = iMX27 FILE = "rootfs.bin", 0x0000000 ;BAD_BLOCKS = 2819, 3067, 3071, 3585 ERASE_BAD_BLOCKS = NO OOB_INFO = IMX_ECC [SERIAL] BAUD=115200 STOP_BITS=1 PARITY=NONE TCP_PORT = 0 ; 2023 [TELNET] PROMPT = "mx27> " ; telnet prompt ;BACKSPACE=127 ; comment out for autodetect [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 25 ; beeper volume [ACTIONS] ; user defined scripts ;AUTORUN = 2 ; executed on every target connect 1 = erase 2 = prog 3 = dump_ram 4 = dump_flash [erase] ; erase flash flash erase [prog] ; program flash flash set 0 flash prog ; program U-BOOT flash set 1 flash prog ; program kernel flash set 2 flash erase ; erase NAND Flash flash prog ; program rootfs [dump_ram] ; dump part of RAM memory dump 0x20000000 0x0100 card:ram.bin