;-------------------------------------------------------------------------- ; ; ; PEEDI sample target configuration file ; ; Ronetix ; ; Supported devices : Marvell 88F6281 ; Board : SheevaPlug ; ; Revision : 1.1 ; ; Date : May 17, 2010 ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. These licenses must be filled before using this file. ; The [LICENSE] section may contain license keys for one or more PEEDIs. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2010, 1111-1111-1111-1 ; KEY = XXXXX, 2222-2222-2222-2 ; ; The [LICENSE] section may point to an external file which contains ; license keys for one or more PEEDIs. The external file must include ; the text [LICENSE] followed by all keys. ; ; Example: ; [LICENSE] ; FILE = tftp://192.168.3.1/license.txt ; or ; FILE=eep:license.txt ; or ; FILE = ftp://user:password@192.168.3.1/license.txt ; ; ; PEEDI is shipped with license keys stored in "eep:license.txt" and ; printed on a label on the bottom side of PEEDI. ; [LICENSE] FILE=eep:license.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote ; gdb remote REMOTE_PORT = 2000 ; TCP/IP port [TARGET] PLATFORM = ARM ; platform is ARM [PLATFORM_ARM] JTAG_CHAIN = 4 ; list of IR lenght of all TAP controller in JTAG chain JTAG_CLOCK = 1000, 25000 ; JTAG Clock in [kHz] - 1MHz jtag clock for init operations and 25MHz for normal work TRST_TYPE = OPENDRAIN ; type of TRST output: OPENDRAIN or PUSHPULL STARTUP_TIME = AUTO ; delay from power-up to reset pulse RESET_TIME = 100 ; lenght of RESET pulse in ms; 0 means no RESET CORE0 = FEROCEON, 0 ; TAP is FEROCEON CPU CORE0_STARTUP_MODE = reset CORE0_BREAKMODE = soft ; breakpoint mode CORE0_BREAK_PATTERN = 0xDFFFDFFF ; software breakpoint pattern CORE0_INIT = INIT_FERO ; init section for EB55800 board CORE0_FLASH0 = NAND_UBOOT ; flash section parameters CORE0_FLASH1 = NAND_KERNEL ; flash section parameters CORE0_FLASH2 = NAND_ROOTFS ; flash section parameters CORE0_ENDIAN = LITTLE ; core is little endian CORE0_WORKSPACE = 0x00000000, 0x10000 ; workspace for flash programmer ;CORE0_VECTOR_CATCH_MASK = 0xFF ; Default path to be used if only a file name (without the full path) is ; provided to a PEEDI command or for the FILE parameter in the Flash sections ; Examples: ; In a console: ; "flash prog tftp://192.168.3.1/image.elf" ; is equal to ; "flash prog image.elf" ; ; In a Flash Profile: ; FILE="tftp://192.168.3.1/image.bin", BIN, 0 ; is equal to ; FILE="image.bin", BIN, 0 ; CORE0_PATH = "tftp://192.168.3.1" ;CORE0_PATH = "card://" CORE0_FILE = "test.bin", BIN, 0x20000000 [INIT_FERO] ; dram init mem wr 0xD0001400 0x43000c30 ; DDR SDRAM Configuration Register mem wr 0xD0001404 0x39543000 ; Dunit Control Low Register mem wr 0xD0001408 0x22125451 ; DDR SDRAM Timing (Low) Register mem wr 0xD000140C 0x00000833 ; DDR SDRAM Timing (High) Register mem wr 0xD0001410 0x000000CC ; DDR SDRAM Address Control Register mem wr 0xD0001414 0x00000000 ; DDR SDRAM Open Pages Control Register mem wr 0xD0001418 0x00000000 ; DDR SDRAM Operation Register mem wr 0xD000141C 0x00000C52 ; DDR SDRAM Mode Register mem wr 0xD0001420 0x00000042 ; DDR SDRAM Extended Mode Register mem wr 0xD0001424 0x0000F1FF ; Dunit Control High Register mem wr 0xD0001428 0x00085520 ; Dunit Control High Register mem wr 0xD000147c 0x00008552 ; Dunit Control High Register mem wr 0xD0001504 0x0FFFFFF1 ; CS[0]n Size Register mem wr 0xD0001508 0x10000000 ; CS[1]n Base Register mem wr 0xD000150C 0x0FFFFFF5 ; CS[1]n Size Register mem wr 0xD0001514 0x00000000 ; CS[2]n Size Register mem wr 0xD000151C 0x00000000 ; CS[3]n Size Register mem wr 0xD0001494 0x003c0000 ; DDR2 SDRAM ODT Control (Low) Register mem wr 0xD0001498 0x00000000 ; DDR2 SDRAM ODT Control (High) Register mem wr 0xD000149C 0x0000F80F ; DDR2 Dunit ODT Control Register mem wr 0xD0001480 0x00000001 ; DDR SDRAM Initialization Control Register mem wr 0xD0020204 0x00000000 ; Main IRQ Interrupt Mask Register mem wr 0xD0020204 0x00000000 ; " mem wr 0xD0020204 0x00000000 ; " mem wr 0xD0020204 0x00000000 ; " mem wr 0xD0020204 0x00000000 ; " mem wr 0xD0020204 0x00000000 ; " mem wr 0xD0020204 0x00000000 ; " mem wr 0xD0020204 0x00000000 ; " mem wr 0xD0020204 0x00000000 ; " mem wr 0xD0020204 0x00000000 ; " mem wr 0xD0020204 0x00000000 ; " mem wr 0xD0020204 0x00000000 ; " mem wr 0xD0020204 0x00000000 ; " mem wr 0xD0020204 0x00000000 ; " mem wr 0xD0020204 0x00000000 ; " mem wr 0xD0020204 0x00000000 ; " mem wr 0xD0020204 0x00000000 ; " mem wr 0xD0020204 0x00000000 ; " mem wr 0xD0020204 0x00000000 ; " mem wr 0xD0020204 0x00000000 ; " mem wr 0xD0020204 0x00000000 ; " mem wr 0xD0020204 0x00000000 ; " mem wr 0xD0020204 0x00000000 ; " mem wr 0xD0020204 0x00000000 ; " mem wr 0xD0020204 0x00000000 ; " mem wr 0xD0020204 0x00000000 ; " mem wr 0xD0020204 0x00000000 ; " mem wr 0xD0020204 0x00000000 ; " mem wr 0xD0020204 0x00000000 ; " mem wr 0xD0020204 0x00000000 ; " mem wr 0xD0020204 0x00000000 ; " mem wr 0xD0020204 0x00000000 ; " mem wr 0xD0020204 0x00000000 ; " mem wr 0xD0020204 0x00000000 ; " mem wr 0xD0020204 0x00000000 ; " mem wr 0xD0020204 0x00000000 ; " mem wr 0xD0020204 0x00000000 ; " ; set MPP pins for NAND mem wr 0xD0010000 0x11111111 mem wr 0xD0010008 0x00001100 [NAND_UBOOT] CHIP = NAND_FLASH DATA_BASE = 0xD8000000 ; data CMD_BASE = 0xD8000001 ; commands (CLE) ADDR_BASE = 0xD8000002 ; addreses (ALE) CS_ASSERT = 0xD0010470, 0x01C7D943 CS_RELEASE = 0xD0010470, 0x01C7D941 BURST_MODE = NO FILE = "card:u-boot.bin", BIN, 0 AUTO_ERASE = YES OOB_INFO = FF [NAND_KERNEL] CHIP = NAND_FLASH DATA_BASE = 0xD8000000 ; data CMD_BASE = 0xD8000001 ; commands (CLE) ADDR_BASE = 0xD8000002 ; addreses (ALE) CS_ASSERT = 0xD0010470, 0x01C7D943 CS_RELEASE = 0xD0010470, 0x01C7D941 BURST_MODE = NO FILE = "card:uImage.bin", BIN, 0x100000 AUTO_ERASE = YES OOB_INFO = JFFS2 [NAND_ROOTFS] CHIP = NAND_FLASH DATA_BASE = 0xD8000000 ; data CMD_BASE = 0xD8000001 ; commands (CLE) ADDR_BASE = 0xD8000002 ; addreses (ALE) CS_ASSERT = 0xD0010470, 0x01C7D943 CS_RELEASE = 0xD0010470, 0x01C7D941 BURST_MODE = NO FILE = "card:rootfs.jfs", BIN, 0x500000 AUTO_ERASE = YES OOB_INFO = JFFS2 [SERIAL] ; serial port configuration BAUD = 115200 STOP_BITS = 1 PARITY = NONE TCP_PORT = 0 [TELNET] PROMPT = "sheeva> " ; telnet prompt ;BACKSPACE = 127 ; comment out for autodetect [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 25 ; zummer volume [ACTIONS] ; user defined scripts 1 = prog_all [prog_all] flash set 0 flash prog flash set 1 flash prog flash set 2 flash prog