;-------------------------------------------------------------------------- ; ; ; PEEDI sample target configuration file showing software emulated SPI ; ; Ronetix ; ; Supported devices : Atmel AT91SAM9263 ; Board : RONETIX PM9263 ; ; Revision : 1.0 ; ; Date : August 27, 2012 ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. ; ; These licenses must be filled before using this file. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2013, 1111-1111-1111-1 ; KEY = ARM7, 2222-2222-2222-2 ; ; The minimum required licenses are provided when PEEDI is purchased and ; are printed on the bottom side of PEEDI. ; [LICENSE] FILE = eep:license.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote ; gdb remote REMOTE_PORT = 2000 ; TCP/IP port [TARGET] PLATFORM = ARM [PLATFORM_ARM] JTAG_CHAIN = 4 ; list of IR lenghts of all TAP controller in JTAG chain JTAG_CLOCK = 5, 20000 ; JTAG Clock in [kHz] - 5kHz jtag clock for init operations and 25MHz for normal work ; Valid range: 5 - 33000 TRST_TYPE = PUSHPULL ; type of TRST output: OPENDRAIN or PUSHPULL RESET_TIME = 20 ; lenght of RESET pulse in ms; 0 means no RESET CORE0 = ARM926E, 0 ; TAP 0 is ARM926E CPU CORE0_STARTUP_MODE = RESET ; startup mode after reset: ; if RESET than no code is executed after reset ; if STOP,XX then the target executes code for XX period in ms. ; if RUN then the target executes code until stopped by the telnet "halt" command CORE0_BREAKMODE = soft ; default breakpoint mode for the debugger: ; soft - use software breakpoints ; hard - use hardware breakpoints CORE_BREAK_PATTERN = 0xDFFFDFFF ; software breakpoint pattern CORE0_INIT = INIT_9263 ; init section CORE0_FLASH0 = SOFT_SPI CORE0_ENDIAN = little CORE0_WORKSPACE_ADDR = 0x20001000 ; start address of workspace for flash programmer CORE0_WORKSPACE_LEN = 0x10000 ; length of workspace in bytes ; Default path to be used if only a file name (without the full path) is ; provided to a PEEDI command or for the FILE parameter in the Flash sections ; Examples: ; In a console: ; "flash prog tftp://192.168.3.1/image.elf" ; is equal to ; "flash prog image.elf" ; ; In a Flash Profile: ; FILE="tftp://192.168.3.1/image.bin", BIN, 0 ; is equal to ; FILE="image.bin", BIN, 0 ; CORE0_PATH = "tftp://192.168.3.1" ;CORE0_PATH = "card://" CORE0_FILE = "test.bin", BIN, 0x20000000 ;------------------------------------------------------------------- ; CORE_VECTOR_CATCH_MASK ; ---------------------- ; If one of the bits is set HIGH and the corresponding exception occurs, the ; processor enters debug state as if a breakpoint has been set on an instruction fetch ; from the relevant exception vector. ; ; bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ;---------------------------------------------------------- ;| fiq | irq | res |d_abort| p_abort| swi | undef | reset | ;---------------------------------------------------------- CORE_VECTOR_CATCH_MASK = 0x00 ;------------------------------------------------- ; Init for Ronetix PM9263 board (CPU: AT91SAM9263) ; In Linux the sys base address 0xFFFFE000 is mapped to 0xFEFFE000 ;------------------------------------------------- [INIT_9263] mem write 0xFFFFFC20 0x00002001 ; CKGR_MOR - enable main osc. mem write 0xFFFFFC28 0x208CBF0D ; CKGR_PLLA - (18.432MHz/13)*141 = 200 MHz ;mem write 0xFFFFFC28 0x20A8BF0D ; CKGR_PLLA - (18.432MHz/13)*169 = 239 MHz wait 100 mem write 0xFFFFFC30 0x00000102 ; PMC_MCKR (MCLK: 0x102 - (239/2)MHZ, 0x202 - (239/4)MHz) clock normal ; switch JTAG clock to 20MHz (the second argument of JTAG_CLOCK) mem write 0xFFFFFD44 0x00008000 ; disable watchdog mem write 0xFFFFFD08 0xA5000301 ; user reset enable mem write 0xFFFFF804 0xFFFF0000 ; define PD[31:16] as DATA[31:16] mem write 0xFFFFF860 0xFFFF0000 ; no pull-up for D[31:16] mem write 0xFFFFED20 0x0001010A ; EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories mem write 0xFFFFED24 0x00010100 ; EBI1_CSA, 3.3V memory ; SDRAM @ addr 0x20000000 mem write 0xFFFFE200 0 ; SDRAMC_MR Mode register mem write 0xFFFFE204 0x13C ; SDRAMC_TR - Refresh Timer register mem write 0xFFFFE208 0x85237279 ; SDRAMC_CR - Configuration register mem write 0xFFFFE224 0 ; Memory Device Register -> SDRAM mem write 0xFFFFE200 0x00000002 ; SDRAMC_MR mem write 0x20000000 0 ; SDRAM_BASE mem write 0xFFFFE200 4 ; SDRC_MR mem write 0x20000000 0 ; SDRAM_BASE mem write 0x20000000 0 ; SDRAM_BASE mem write 0x20000000 0 ; SDRAM_BASE mem write 0x20000000 0 ; SDRAM_BASE mem write 0x20000000 0 ; SDRAM_BASE mem write 0x20000000 0 ; SDRAM_BASE mem write 0x20000000 0 ; SDRAM_BASE mem write 0x20000000 0 ; SDRAM_BASE mem write 0xFFFFE200 3 ; SDRC_MR mem write 0x20000000 0 ; SDRAM_BASE mem write 0xFFFFE200 0 ; SDRC_MR mem write 0x20000000 0 ; SDRAM_BASE mem write 0xFFFFE204 1200 ; SDRAM_TR mem write 0x20000000 0 ; SDRAM_BASE ; enable all peripheral clocks mem write 0xFFFFFC10 0xFFFFFFFF ; PMC_PCER ; setup EBI0_CS0 (NOR Flash) - 16-bit, 15 WS @ addr 0x10000000 mem write 0xFFFFE400 0x03030303 ; SMC_SETUP mem write 0xFFFFE404 0x09090909 ; SMC_PULSE mem write 0xFFFFE408 0x00120012 ; SMC_CYCLE mem write 0xFFFFE40C 0x00161003 ; SMC_MODE ; setup PB29 as output mem write 0xFFFFF400 0x20000000 mem write 0xFFFFF410 0x20000000 ; PIOC->PER <- PB29 mem write 0xFFFFF430 0x20000000 ; PIOC->SODR, set PB29 to '1' - MT45W2MW16A, FMP3216CA5 ;mem write 0xFFFFF434 0x20000000 ; PIOC->SODR, set PB29 to '0' - MT45W2MW16B ; setup EBI1_CS0 (PSRAM): 16-bit, 15 WS @ addr 0x70000000 mem write 0xFFFFEA00 0x0A0A0A0A ; SMC_SETUP mem write 0xFFFFEA04 0x0B0B0B0B ; SMC_PULSE mem write 0xFFFFEA08 0x00160016 ; SMC_CYCLE ;mem write 0xFFFFEA0C 0x00161003 ; SMC_MODE, async mode mem write 0xFFFFEA0C 0x31161003 ; SMC_MODE, page mode ; PSRAM: read BCR ;mem r16 0x703ffffe 1 ;mem r16 0x703ffffe 1 ;mem w16 0x703ffffe 1 ; 0 for RCR, 1 for BCR ;mem r16 0x703ffffe 1 ; read the BCR ; PSRAM: write BCR mem r16 0x703ffffe 1 mem r16 0x703ffffe 1 mem w16 0x703ffffe 1 ; 0 for RCR, 1 for BCR mem w16 0x703ffffe 0x9D4F ; read the BCR ; PSRAM: write RCR mem r16 0x703ffffe 1 mem r16 0x703ffffe 1 mem w16 0x703ffffe 0 ; 0 for RCR, 1 for BCR mem w16 0x703ffffe 0x90 ; set RCR; 0x10 - async mode, 0x90 - page mode ; setup CS3 (NAND Flash) - 16-bit mem write 0xFFFFE430 0x03030303 ; SMC_SETUP mem write 0xFFFFE434 0x04040404 ; SMC_PULSE mem write 0xFFFFE438 0x00080008 ; SMC_CYCLE ;mem write 0xFFFFE43C 0x00161003 ; SMC_MODE ; 16-bit mem write 0xFFFFE43C 0x00160003 ; SMC_MODE ; 8-bit ; NAND FLash: configure PIOs in periph mode mem write 0xFFFFF800 0x8000 mem write 0xFFFFF810 0x8000 ; PIOC->PER <- PD15 mem write 0xFFFFF830 0x8000 ; PIOC->SODR, set PD15 to '1' mem write 0xFFFFED00 0x3 ; MATRIX_MCFG - REMAP all masters set control 0x5107C ; enable ICache and Dcache ;set control 0x78 ; disable ICache and Dcache set cpsr 0xd3 set pc 0x10000040 ; set SPI pins as GPIOs m w 0xFFFFF210 0x00000026 ; set PA1 (MOSI), PA2 (SCK), PA5 (/CS) as outputs. (PIO_OER) m w 0xFFFFF230 0x00000020 ; set the output data on PA5 used for /CS. (PIO_SODR) m w 0xFFFFF410 0x00000180 ; enable the output on PB8 : 7 (PIO_OER) LED debug wait 100 m w 0xFFFFF430 0x00000180 ; turn off both LEDs [SOFT_SPI] CHIP = AT45_DATAFLASH ; the DataFlash chip will be autodetected CPU = GENERIC_SPI CS_ASSERT = 0xFFFFF234 equ 0x00000020 ; clear PA5 CS_RELEASE = 0xFFFFF230 equ 0x00000020 ; set PA5 MOSI_SET = 0xFFFFF230 equ 0x00000002 ; set PA1 MOSI_CLR = 0xFFFFF234 equ 0x00000002 ; clear PA1 SCLK_SET = 0xFFFFF234 equ 0x00000004 ; clear PA2 SCLK_CLR = 0xFFFFF230 equ 0x00000004 ; set PA2 MISO_READ = 0xFFFFF23C and 0x00000001 ; get PA0 FILE = myfile.bin, 0 [SERIAL] BAUD=115200 STOP_BITS=1 PARITY=NONE TCP_PORT = 0 ; enable CLI over RS232 ;TCP_PORT = 2023 ; enable serial over TCP/IP [TELNET] PROMPT = "PM9263> " ; telnet prompt ;BACKSPACE=127 ; comment out for autodetect [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 25 ; beeper volume ; ; Scripts to be executed using front panel buttons ; If AUTORUN is specified, the given script will be executed every time ; a target is connected to PEEDI ; [ACTIONS] ; user defined scripts ;AUTORUN = 2 ; executed on every target connect 1 = erase 2 = prog [erase] ; erase flash flash erase ; Program all Linux images ; To use the script type in the console: ; run $prog ; [prog] flash prog ; program U-BOOT