;-------------------------------------------------------------------------- ; ; ; PEEDI sample target configuration file ; ; Ronetix ; ; Supported devices : Atmel AT91SAM9263 ; Board : 4 x RONETIX PM9263 ; ; Revision : 1.0 ; ; Date : May 13, 2010 ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. These licenses must be filled before using this file. ; The [LICENSE] section may contain license keys for one or more PEEDIs. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2010, 1111-1111-1111-1 ; KEY = XXXXX, 2222-2222-2222-2 ; ; The [LICENSE] section may point to an external file which contains ; license keys for one or more PEEDIs. The external file must include ; the text [LICENSE] followed by all keys. ; ; Example: ; [LICENSE] ; FILE = tftp://192.168.3.1/license.txt ; or ; FILE=eep:license.txt ; or ; FILE = ftp://user:password@192.168.3.1/license.txt ; ; ; PEEDI is shipped with license keys stored in "eep:license.txt" and ; printed on a label on the bottom side of PEEDI. ; [LICENSE] FILE=eep:license.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote ; gdb remote REMOTE_PORT = 2000 ; TCP/IP port [TARGET] PLATFORM = ARM [PLATFORM_ARM] JTAG_CHAIN = 4, 4, 4, 4 ; list of IR lenghts of all TAP controller in JTAG chain JTAG_CLOCK = 5, 10000 ; JTAG Clock in [kHz] - 5kHz jtag clock for init operations and 10MHz for normal work TRST_TYPE = PUSHPULL ; type of TRST output: OPENDRAIN or PUSHPULL RESET_TIME = 20 ; lenght of RESET pulse in ms; 0 means no RESET TIME_AFTER_RESET = 500 CORE0 = ARM926E, 0 ; TAP 0 is ARM926E CPU CORE0_STARTUP_MODE = RESET ; startup mode after reset CORE0_BREAKMODE = soft ; default breakpoint mode for the debugger: CORE0_BREAK_PATTERN = 0xDFFFDFFF ; software breakpoint pattern CORE0_INIT = INIT_9263 ; init section CORE0_FLASH0 = U-BOOT CORE0_FLASH1 = KERNEL CORE0_FLASH2 = ROOTFS_NAND CORE0_FLASH3 = DATAFLASH CORE0_FLASH4 = WINCE-NOR CORE0_FLASH5 = WINCE_BOOT_NAND CORE0_FLASH6 = WINCE_KERNEL_NAND CORE0_ENDIAN = little CORE0_WORKSPACE_ADDR = 0x20001000 ; start address of workspace for flash programmer CORE0_WORKSPACE_LEN = 0x10000 ; length of workspace in bytes CORE0_PATH = "card://" CORE0_FILE = "test.bin", BIN, 0x20000000 CORE0_VECTOR_CATCH_MASK = 0x00 CORE1 = ARM926E, 1 ; TAP 0 is ARM926E CPU CORE1_STARTUP_MODE = RESET ; startup mode after reset CORE1_BREAKMODE = soft ; default breakpoint mode for the debugger: CORE1_BREAK_PATTERN = 0xDFFFDFFF ; software breakpoint pattern CORE1_INIT = INIT_9263 ; init section CORE1_FLASH0 = U-BOOT CORE1_FLASH1 = KERNEL CORE1_FLASH2 = ROOTFS_NAND CORE1_FLASH3 = DATAFLASH CORE1_FLASH4 = WINCE-NOR CORE1_FLASH5 = WINCE_BOOT_NAND CORE1_FLASH6 = WINCE_KERNEL_NAND CORE1_ENDIAN = little CORE1_WORKSPACE_ADDR = 0x20001000 ; start address of workspace for flash programmer CORE1_WORKSPACE_LEN = 0x10000 ; length of workspace in bytes CORE1_PATH = "card://" CORE1_FILE = "test.bin", BIN, 0x20000000 CORE1_VECTOR_CATCH_MASK = 0x00 CORE2 = ARM926E, 2 ; TAP 0 is ARM926E CPU CORE2_STARTUP_MODE = RESET ; startup mode after reset CORE2_BREAKMODE = soft ; default breakpoint mode for the debugger: CORE2_BREAK_PATTERN = 0xDFFFDFFF ; software breakpoint pattern CORE2_INIT = INIT_9263 ; init section CORE2_FLASH0 = U-BOOT CORE2_FLASH1 = KERNEL CORE2_FLASH2 = ROOTFS_NAND CORE2_FLASH3 = DATAFLASH CORE2_FLASH4 = WINCE-NOR CORE2_FLASH5 = WINCE_BOOT_NAND CORE2_FLASH6 = WINCE_KERNEL_NAND CORE2_ENDIAN = little CORE2_WORKSPACE_ADDR = 0x20001000 ; start address of workspace for flash programmer CORE2_WORKSPACE_LEN = 0x10000 ; length of workspace in bytes CORE2_PATH = "card://" CORE2_FILE = "test.bin", BIN, 0x20000000 CORE2_VECTOR_CATCH_MASK = 0x00 CORE3 = ARM926E, 3 ; TAP 0 is ARM926E CPU CORE3_STARTUP_MODE = RESET ; startup mode after reset CORE3_BREAKMODE = soft ; default breakpoint mode for the debugger: CORE3_BREAK_PATTERN = 0xDFFFDFFF ; software breakpoint pattern CORE3_INIT = INIT_9263 ; init section CORE3_FLASH0 = U-BOOT CORE3_FLASH1 = KERNEL CORE3_FLASH2 = ROOTFS_NAND CORE3_FLASH3 = DATAFLASH CORE3_FLASH4 = WINCE-NOR CORE3_FLASH5 = WINCE_BOOT_NAND CORE3_FLASH6 = WINCE_KERNEL_NAND CORE3_ENDIAN = little CORE3_WORKSPACE_ADDR = 0x20001000 ; start address of workspace for flash programmer CORE3_WORKSPACE_LEN = 0x10000 ; length of workspace in bytes CORE3_PATH = "card://" CORE3_FILE = "test.bin", BIN, 0x20000000 CORE3_VECTOR_CATCH_MASK = 0x00 ;------------------------------------------------- ; Init for Ronetix PM9263 board (CPU: AT91SAM9263) ; In Linux the sys base address 0xFFFFE000 is mapped to 0xFEFFE000 ;------------------------------------------------- [INIT_9263] mem write 0xFFFFFC20 0x00002001 ; CKGR_MOR - enable main osc. mem write 0xFFFFFC28 0x208CBF0D ; CKGR_PLLA - (18.432MHz/13)*141 = 200 MHz ;mem write 0xFFFFFC28 0x20A8BF0D ; CKGR_PLLA - (18.432MHz/13)*169 = 239 MHz wait 100 mem write 0xFFFFFC30 0x00000102 ; PMC_MCKR (MCLK: 0x102 - (239/2)MHZ, 0x202 - (239/4)MHz) mem write 0xFFFFFD44 0x00008000 ; disable watchdog mem write 0xFFFFFD08 0xA5000301 ; user reset enable mem write 0xFFFFF804 0xFFFF0000 ; define PD[31:16] as DATA[31:16] mem write 0xFFFFF860 0xFFFF0000 ; no pull-up for D[31:16] mem write 0xFFFFED20 0x0001010A ; EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories mem write 0xFFFFED24 0x00010100 ; EBI1_CSA, 3.3V memory ; SDRAM @ addr 0x20000000 mem write 0xFFFFE200 0 ; SDRAMC_MR Mode register mem write 0xFFFFE204 0x13C ; SDRAMC_TR - Refresh Timer register mem write 0xFFFFE208 0x85237279 ; SDRAMC_CR - Configuration register mem write 0xFFFFE224 0 ; Memory Device Register -> SDRAM mem write 0xFFFFE200 0x00000002 ; SDRAMC_MR mem write 0x20000000 0 ; SDRAM_BASE mem write 0xFFFFE200 4 ; SDRC_MR mem write 0x20000000 0 ; SDRAM_BASE mem write 0x20000000 0 ; SDRAM_BASE mem write 0x20000000 0 ; SDRAM_BASE mem write 0x20000000 0 ; SDRAM_BASE mem write 0x20000000 0 ; SDRAM_BASE mem write 0x20000000 0 ; SDRAM_BASE mem write 0x20000000 0 ; SDRAM_BASE mem write 0x20000000 0 ; SDRAM_BASE mem write 0xFFFFE200 3 ; SDRC_MR mem write 0x20000000 0 ; SDRAM_BASE mem write 0xFFFFE200 0 ; SDRC_MR mem write 0x20000000 0 ; SDRAM_BASE mem write 0xFFFFE204 1200 ; SDRAM_TR mem write 0x20000000 0 ; SDRAM_BASE ; enable all peripheral clocks mem write 0xFFFFFC10 0xFFFFFFFF ; PMC_PCER ; setup EBI0_CS0 (NOR Flash) - 16-bit, 15 WS @ addr 0x10000000 mem write 0xFFFFE400 0x03030303 ; SMC_SETUP mem write 0xFFFFE404 0x09090909 ; SMC_PULSE mem write 0xFFFFE408 0x00120012 ; SMC_CYCLE mem write 0xFFFFE40C 0x00161003 ; SMC_MODE ; setup PB29 as output mem write 0xFFFFF400 0x20000000 mem write 0xFFFFF410 0x20000000 ; PIOC->PER <- PB29 mem write 0xFFFFF434 0x20000000 ; PIOC->SODR, set PB29 to '0' ; setup EBI1_CS0 (PSRAM): 16-bit, 15 WS @ addr 0x70000000 mem write 0xFFFFEA00 0x0A0A0A0A ; SMC_SETUP mem write 0xFFFFEA04 0x0B0B0B0B ; SMC_PULSE mem write 0xFFFFEA08 0x00160016 ; SMC_CYCLE ;mem write 0xFFFFEA0C 0x00161003 ; SMC_MODE, async mode mem write 0xFFFFEA0C 0x31161003 ; SMC_MODE, page mode ; PSRAM: read BCR ;mem r16 0x703ffffe 1 ;mem r16 0x703ffffe 1 ;mem w16 0x703ffffe 1 ; 0 for RCR, 1 for BCR ;mem r16 0x703ffffe 1 ; read the BCR ; PSRAM: write BCR mem r16 0x703ffffe 1 mem r16 0x703ffffe 1 mem w16 0x703ffffe 1 ; 0 for RCR, 1 for BCR mem w16 0x703ffffe 0x9D4F ; read the BCR ; PSRAM: write RCR mem r16 0x703ffffe 1 mem r16 0x703ffffe 1 mem w16 0x703ffffe 0 ; 0 for RCR, 1 for BCR mem w16 0x703ffffe 0x90 ; set RCR; 0x10 - async mode, 0x90 - page mode ; setup CS3 (NAND Flash) - 16-bit mem write 0xFFFFE430 0x03030303 ; SMC_SETUP mem write 0xFFFFE434 0x04040404 ; SMC_PULSE mem write 0xFFFFE438 0x00080008 ; SMC_CYCLE ;mem write 0xFFFFE43C 0x00161003 ; SMC_MODE ; 16-bit mem write 0xFFFFE43C 0x00160003 ; SMC_MODE ; 8-bit ; NAND FLash: configure PIOs in periph mode mem write 0xFFFFF800 0x8000 mem write 0xFFFFF810 0x8000 ; PIOC->PER <- PD15 mem write 0xFFFFF830 0x8000 ; PIOC->SODR, set PD15 to '1' mem write 0xFFFFED00 0x3 ; MATRIX_MCFG - REMAP all masters set control 0x5107C ; enable ICache and Dcache ;set control 0x78 ; disable ICache and Dcache set cpsr 0xd3 set pc 0x10000040 [U-BOOT] CHIP = S29GL032MB CHIP = AT49BV322A CHIP = ES29LV320EB ACCESS_METHOD = AGENT CHECK_ID = YES CHIP_WIDTH = 16 CHIP_COUNT = 1 BASE_ADDR = 0x10000000 FILE="eb9263/u-boot.bin", BIN, 0x10000000 ;FILE="card:u-boot.bin", BIN, 0x10000000 AUTO_ERASE=YES [KERNEL] CHIP = S29GL032MB CHIP = AT49BV322A CHIP = ES29LV320EB ACCESS_METHOD = AGENT CHECK_ID = YES CHIP_WIDTH = 16 CHIP_COUNT = 1 BASE_ADDR = 0x10000000 FILE="eb9263/vmImage.bin", BIN, 0x10050000 ;FILE="card:vmImage.bin", BIN, 0x10050000 AUTO_ERASE=YES [DATAFLASH] CHIP = AT45_DATAFLASH ; the DataFlash chip will be autodetected CPU = AT91SAM9263 ; AT91 CPU type: AT91RM9200, AT91SAM9261, AT91SAM9263 or AT91SAM7 SPI_DIV = 8 ; AT91RM9200: Fspi = (MCK/2)/SPI_DIV; AT91SAM9261: Fspi = MCK/SPI_DIV; nSPI = 0 ; which SPI controller: 0 or 1 nCS = 0 ; which chip select: 0 - 3 SPI_SPCK = PIOA, B, 2 ; pin definition for SPCK: PIOA, peripheral B, io2 SPI_MISO = PIOA, B, 0 ; pin definition for MISO: PIOA, peripheral B, io0 SPI_MOSI = PIOA, B, 1 ; pin definition for MOSI: PIOA, peripheral B, io1 SPI_CS = PIOA, B, 5 ; pin definition for CS : PIOA, peripheral B, io5 FILE = "test.bin", BIN, 0 [ROOTFS_NAND] CHIP = NAND_FLASH DATA_BASE = 0x40000000 ; data CMD_BASE = 0x40400000 ; addreses (CLE) ADDR_BASE = 0x40200000 ; commands (ALE) FILE = "eb9263/rootfs.jffs2", BIN, 0 ;FILE = "ftp://user:password@192.168.3.1/rootfs.jffs2", BIN, 0 ;FILE = "card:rootfs.jfs", BIN, 0 ; address and value for asserting the Nand Flash Chip select ; [addr] = value CS_ASSERT = 0xFFFFF834, 0x8000 ; address and value for releasing the Nand Flash Chip select ; [addr] = value CS_RELEASE = 0xFFFFF830, 0x8000 ; list with bad blocks to be marked as bad ;========================================= ;BAD_BLOCKS=1146, 1698 ; CAUTION!!! ; Enable erasing of bad blocks ; DO NOT Enable this if you don't know what you are doing ; For more information see the AN006 (www.ronetix.at/an006.html) ERASE_BAD_BLOCKS = NO OOB_INFO = JFFS2 ; how to deal with the OOB (spare) info ; RAW - program 528/2112 bytes from file ; JFFS2 - program 512/2048 bytes from file and add ECC bytes ; FF - program 512/2048 bytes from file, set spare info to 0xFF [WINCE-NOR] CHIP = S29GL032MB ACCESS_METHOD = AGENT CHECK_ID = YES CHIP_WIDTH = 16 CHIP_COUNT = 1 BASE_ADDR = 0x10000000 FILE="eb9263/wince60/nor_loader.bin", BIN, 0x10000000 AUTO_ERASE=YES [WINCE_BOOT_NAND] CHIP = NAND_FLASH DATA_BASE = 0x40000000 ; data CMD_BASE = 0x40400000 ; addreses (CLE) ADDR_BASE = 0x40200000 ; commands (ALE) FILE = "eb9263/wince60/EBOOT_verbose.nb0", BIN, 0x20000 CS_ASSERT = 0xFFFFF834, 0x8000 CS_RELEASE = 0xFFFFF830, 0x8000 ERASE_BAD_BLOCKS = NO OOB_INFO = JFFS2 [WINCE_KERNEL_NAND] CHIP = NAND_FLASH DATA_BASE = 0x40000000 ; data CMD_BASE = 0x40400000 ; addreses (CLE) ADDR_BASE = 0x40200000 ; commands (ALE) FILE = "eb9263/wince60/NK.nb0", BIN, 0x80000 CS_ASSERT = 0xFFFFF834, 0x8000 CS_RELEASE = 0xFFFFF830, 0x8000 ERASE_BAD_BLOCKS = NO OOB_INFO =JFFS2 [SERIAL] BAUD=115200 STOP_BITS=1 PARITY=NONE TCP_PORT = 0 ; enable CLI over RS232 ;TCP_PORT = 2023 ; enable serial over TCP/IP [TELNET] PROMPT = "PM9263> " ; telnet prompt ;BACKSPACE=127 ; comment out for autodetect [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 25 ; beeper volume ; ; Scripts to be executed using front panel buttons ; If AUTORUN is specified, the given script will be executed every time ; a target is connected to PEEDI ; [ACTIONS] ; user defined scripts ;AUTORUN = 2 ; executed on every target connect 1 = erase 2 = prog 3 = dump_ram 4 = dump_flash 5 = wince [erase] ; erase flash flash multi erase ; Program all Linux images ; To use the script type in the console: ; run $prog ; [prog] flash set 0 flash multi erase flash multi prog ; program U-BOOT flash set 1 flash multi prog ; program kernel flash set 2 flash multi erase ; erase NAND Flash flash multi prog ; program rootfs ; Program all WinCE images ; To use the script type in the console: ; run $wince ; [wince] flash set 4 flash multi erase flash multi prog flash set 5 flash multi erase flash multi prog flash set 6 flash multi prog [dump_ram] ; dump part of RAM memory dump 0x20000000 0x0100 card:ram.bin