;-------------------------------------------------------------------------- ; ; ; PEEDI sample target configuration file ; ; Ronetix ; ; Supported devices : Atmel AT91SAM9261 ; Board : RONETIX PM9261 ; ; Revision : 1.2 ; ; Date : May 12, 2010 ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. These licenses must be filled before using this file. ; The [LICENSE] section may contain license keys for one or more PEEDIs. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2010, 1111-1111-1111-1 ; KEY = XXXXX, 2222-2222-2222-2 ; ; The [LICENSE] section may point to an external file which contains ; license keys for one or more PEEDIs. The external file must include ; the text [LICENSE] followed by all keys. ; ; Example: ; [LICENSE] ; FILE = tftp://192.168.3.1/license.txt ; or ; FILE=eep:license.txt ; or ; FILE = ftp://user:password@192.168.3.1/license.txt ; ; ; PEEDI is shipped with license keys stored in "eep:license.txt" and ; printed on a label on the bottom side of PEEDI. ; [LICENSE] FILE=eep:license.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote ; gdb remote REMOTE_PORT = 2000 ; TCP/IP port [TARGET] PLATFORM = ARM [PLATFORM_ARM] JTAG_CHAIN = 4 ; list of IR lenghts of all TAP controller in JTAG chain JTAG_CLOCK = 5, 20000 ; JTAG Clock in [kHz] - 5kHz jtag clock for init operations and 20MHz for normal work ; Valid range: 5 - 33000 TRST_TYPE = PUSHPULL ; type of TRST output: OPENDRAIN or PUSHPULL RESET_TIME = 20 ; lenght of RESET pulse in ms; 0 means no RESET CORE0 = ARM926E, 0 ; TAP 0 is ARM926E CPU CORE0_STARTUP_MODE = RESET ; startup mode after reset: ; if RESET than no code is executed after reset ; if STOP,XX then the target executes code for XX period in ms. ; if RUN then the target executes code until stopped by the telnet "halt" command CORE0_BREAKMODE = soft ; default breakpoint mode for the debugger: ; soft - use software breakpoints ; hard - use hardware breakpoints CORE_BREAK_PATTERN = 0xDFFFDFFF ; software breakpoint pattern CORE0_INIT = INIT_9261 ; init section CORE0_FLASH0 = U-BOOT CORE0_FLASH1 = KERNEL CORE0_FLASH2 = ROOTFS_NAND CORE0_FLASH3 = DATAFLASH CORE0_FLASH4 = REDBOOT CORE0_FLASH5 = ECOS_EXAMPLE CORE0_ENDIAN = little CORE0_WORKSPACE_ADDR = 0x20001000 ; start address of workspace for flash programmer CORE0_WORKSPACE_LEN = 0x10000 ; length of workspace in bytes ; Default path to be used if only a file name (without the full path) is ; provided to a PEEDI command or for the FILE parameter in the Flash sections ; Examples: ; In a console: ; "flash prog tftp://192.168.3.1/image.elf" ; is equal to ; "flash prog image.elf" ; ; In a Flash Profile: ; FILE="tftp://192.168.3.1/image.bin", BIN, 0 ; is equal to ; FILE="image.bin", BIN, 0 ; CORE0_PATH = "tftp://192.168.3.1" ;CORE0_PATH = "card://" CORE0_FILE = "test.bin", BIN, 0x20000000 ;------------------------------------------------------------------- ; CORE_VECTOR_CATCH_MASK ; ---------------------- ; If one of the bits is set HIGH and the corresponding exception occurs, the ; processor enters debug state as if a breakpoint has been set on an instruction fetch ; from the relevant exception vector. ; ; bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ;---------------------------------------------------------- ;| fiq | irq | res |d_abort| p_abort| swi | undef | reset | ;---------------------------------------------------------- CORE_VECTOR_CATCH_MASK = 0x00 ;------------------------------------------------- ; Init for Ronetix PM9261 board (CPU: AT91SAM9261) ;------------------------------------------------- [INIT_9261] mem write 0xFFFFFC20 0x00002001 ; CKGR_MOR - enable main osc. ;mem write 0xFFFFFC28 0x200CBF01 ; CKGR_PLLA - (18.432MHz/1)*13 = 239 MHz mem write 0xFFFFFC28 0x208CBF0D ; CKGR_PLLA - (18.432MHz/13)*141 = 199.9 MHz wait 100 ; delay 100ms mem write 0xFFFFFC30 0x00000102 ; PMC_MCKR (MCLK: 0x102 - (CLK/2)MHZ, 0x202 - (CLK/3)MHz) ; switch JTAG clock to 20MHz (the second argument of JTAG_CLOCK) clock normal ; remove this when INIT used for multicore mem write 0xfffffd44 0x3fff8fff ; disable watchdog mem write 0xFFFFFD08 0xA5000001 ; user reset enable mem write 0xFFFFF804 0xFFFF0000 ; define PDC[31:16] as DATA[31:16] mem write 0xFFFFF860 0xFFFF0000 ; no pull-up for D[31:16] mem write 0xFFFFEE30 0x10A ; EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash mem write 0xFFFFEA00 0 ; SDRAMC_MR Mode register mem write 0xFFFFEA04 0x13C ; SDRAMC_TR - Refresh Timer register mem write 0xFFFFEA08 0x85237279 ; SDRAMC_CR - Configuration register mem write 0xFFFFEA24 0 ; Memory Device Register -> SDRAM mem write 0xFFFFEA00 0x00000002 ; SDRAMC_MR mem write 0x20000000 0 ; SDRAM_BASE mem write 0xFFFFEA00 4 ; SDRC_MR mem write 0x20000000 0 ; SDRAM_BASE mem write 0x20000000 0 ; SDRAM_BASE mem write 0x20000000 0 ; SDRAM_BASE mem write 0x20000000 0 ; SDRAM_BASE mem write 0x20000000 0 ; SDRAM_BASE mem write 0x20000000 0 ; SDRAM_BASE mem write 0x20000000 0 ; SDRAM_BASE mem write 0x20000000 0 ; SDRAM_BASE mem write 0xFFFFEA00 3 ; SDRC_MR mem write 0x20000000 0 ; SDRAM_BASE mem write 0xFFFFEA00 0 ; SDRC_MR mem write 0x20000000 0 ; SDRAM_BASE mem write 0xFFFFEA04 1200 ; SDRAM_TR mem write 0x20000000 0 ; SDRAM_BASE ; setup CS0 (NOR Flash) - 16-bit, 15 WS mem write 0xFFFFEC00 0x0A0A0A0A ; SMC_SETUP mem write 0xFFFFEC04 0x0B0B0B0B ; SMC_PULSE mem write 0xFFFFEC08 0x00160016 ; SMC_CYCLE mem write 0xFFFFEC0C 0x00161003 ; SMC_MODE ; setup CS3 (NAND Flash) - 8/16-bit mem write 0xFFFFEC30 0x03030303 ; SMC_SETUP mem write 0xFFFFEC34 0x04040404 ; SMC_PULSE mem write 0xFFFFEC38 0x00080008 ; SMC_CYCLE ;mem write 0xFFFFEC3C 0x00161003 ; SMC_MODE 16-bit mem write 0xFFFFEC3C 0x00160003 ; SMC_MODE 8-bit ; NAND FLash: configure PIOs in periph mode mem write 0xFFFFF870 3 ; PIOC->ASR <- PC0 | PC1 mem write 0xFFFFF874 0 ; PIOC->BSR mem write 0xFFFFF804 3 ; PIOC->PDR <- PC0 | PC1 mem write 0xFFFFF800 0x4000 mem write 0xFFFFF810 0x4000 ; PIOC->PER <- PC14 mem write 0xFFFFF830 0x4000 ; PIOC->SODR, set PC14 to '1' ; serial DBGU init (for linux debuging) mem write 0xFFFFF404 0xc00 ; PA 10 & 9 for DBGU mem write 0xFFFFFC10 1 ; enable clock mem write 0xFFFFF220 0x41 ; 115200 mem write 0xFFFFF200 0xc mem write 0xFFFFF200 0x50 mem write 0xFFFFF204 0x8c0 mem write 0xFFFFF210 0xffffffff mem write 0xFFFFEE00 0xF ; MATRIX_MCFG - REMAP all masters set control 0x5107C ; enable ICache and Dcache set cpsr 0xd3 set pc 0x10000040 [U-BOOT] CHIP = CFI_FLASH ACCESS_METHOD = AGENT BASE_ADDR = 0x10000000 FILE="eb9261/u-boot.bin", BIN, 0x10000000 AUTO_ERASE = NO [KERNEL] CHIP = CFI_FLASH BASE_ADDR = 0x10000000 FILE="eb9261/uImage", BIN, 0x10050000 ;FILE="card:uimage.bin", BIN, 0x10050000 AUTO_ERASE=YES [DATAFLASH] CHIP = AT45_DATAFLASH ; the DataFlash chip will be autodetected CPU = AT91SAM9261 ; AT91 CPU type: AT91RM9200, AT91SAM9261 or AT91SAM7 SPI_DIV = 8 ; AT91RM9200: Fspi = (MCK/2)/SPI_DIV; AT91SAM9261: Fspi = MCK/SPI_DIV; nSPI = 0 ; which SPI controller: 0 or 1 nCS = 0 ; which chip select: 0 - 3 SPI_SPCK = PIOA, A, 2 ; pin definition for SPCK: PIOA, peripheral A, io2 SPI_MISO = PIOA, A, 0 ; pin definition for MISO: PIOA, peripheral A, io0 SPI_MOSI = PIOA, A, 1 ; pin definition for MOSI: PIOA, peripheral A, io1 SPI_CS = PIOA, A, 3 ; pin definition for CS : PIOA, peripheral A, io3 FILE = "test.bin", BIN, 0 [ROOTFS_NAND] CHIP = NAND_FLASH DATA_BASE = 0x40000000 ; data CMD_BASE = 0x40200000 ; commands (CLE) ADDR_BASE = 0x40400000 ; addreses (ALE) FILE = "eb9261/rootfs.jffs2", BIN, 0 ;FILE = "ftp://user:password@192.168.3.1/rootfs.jffs2", BIN, 0 ;FILE = "card:rootfs.jfs", BIN, 0 ; address and value for asserting the Nand Flash Chip select ; [addr] = value CS_ASSERT = 0xFFFFF834, 0x4000 ; address and value for releasing the Nand Flash Chip select ; [addr] = value CS_RELEASE = 0xFFFFF830, 0x4000 ; list with bad blocks to be marked as bad ;========================================= ;BAD_BLOCKS=1146, 1698 ; CAUTION!!! ; Enable erasing of bad blocks ; DO NOT Enable this if you don't know what you are doing ; For more information see the AN006 (www.ronetix.at/an006.html) ERASE_BAD_BLOCKS = NO OOB_INFO = JFFS2 ; how to deal with the OOB (spare) info ; RAW - program 528/2112 bytes from file ; JFFS2 - program 512/2048 bytes from file and add ECC bytes ; FF - program 512/2048 bytes from file, set spare info to 0xFF [REDBOOT] CHIP = S29GL032MB ACCESS_METHOD = AGENT CHECK_ID = YES CHIP_WIDTH = 16 CHIP_COUNT = 1 BASE_ADDR = 0x10000000 FILE="tftp:eb9261/redboot.bin", BIN, 0x10000000 AUTO_ERASE=YES [ECOS_EXAMPLE] CHIP = S29GL032MB ACCESS_METHOD = AGENT CHECK_ID = YES CHIP_WIDTH = 16 CHIP_COUNT = 1 BASE_ADDR = 0x10000000 FILE="tftp:eb9261/main.bin", BIN, 0x10000000 AUTO_ERASE=YES [SERIAL] BAUD=115200 STOP_BITS=1 PARITY=NONE TCP_PORT = 0 ; enable CLI over RS232 ;TCP_PORT = 2023 ; enable serial over TCP/IP [TELNET] PROMPT = "PM9261> " ; telnet prompt ;BACKSPACE=127 ; comment out for autodetect [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 25 ; beeper volume [ACTIONS] ; user defined scripts ;AUTORUN = 2 ; executed on every target connect 1 = erase 2 = prog 3 = dump_ram 4 = dump_flash [erase] ; erase flash flash erase [prog] ; program flash flash set 0 flash prog ; program U-BOOT flash set 1 flash prog ; program kernel flash set 2 flash erase ; erase NAND Flash flash prog ; program rootfs [dump_ram] ; dump part of RAM memory dump 0x20000000 0x0100 card:ram.bin