;-------------------------------------------------------------------------- ; ; ; PEEDI sample target configuration file ; ; Ronetix ; ; Supported devices : Freescale iMX35, ARM1136 ; ; Board : Custom - booting from eMMC ; ; Revision : 1.0 ; ; Date : Dec 20, 2010 ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. These licenses must be filled before using this file. ; The [LICENSE] section may contain license keys for one or more PEEDIs. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2010, 1111-1111-1111-1 ; KEY = XXXXX, 2222-2222-2222-2 ; ; The [LICENSE] section may point to an external file which contains ; license keys for one or more PEEDIs. The external file must include ; the text [LICENSE] followed by all keys. ; ; Example: ; [LICENSE] ; FILE = tftp://192.168.3.1/license.txt ; or ; FILE=eep:license.txt ; or ; FILE = ftp://user:password@192.168.3.1/license.txt ; ; ; PEEDI is shipped with license keys stored in "eep:license.txt" and ; printed on a label on the bottom side of PEEDI. ; [LICENSE] FILE = eep:license.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote ; gdb remote REMOTE_PORT = 2000 ; TCP/IP port GDB_READ_INGNORE_TIME = 3000 [TARGET] PLATFORM = ARM11 ; platform is ARM11 [PLATFORM_ARM11] JTAG_CHAIN = 5, 4, 5, 4 ; list of IR lenght of all TAP controllers in JTAG chain JTAG_CLOCK = 1000, 25000 ; JTAG Clock in [kHz] - 10kHz jtag clock for init operations and 10MHz for normal work JTAG_TDO_DELAY = AUTO TRST_TYPE = OPENDRAIN ; type of TRST output: OPENDRAIN or PUSHPULL RESET_TIME = 200 ; lenght of RESET pulse in ms; 0 means no RESET CORE0 = ARM1136, 2 ; TAP is ARM11 CPU CORE0_BREAKMODE = soft ; breakpoint mode CORE0_INIT = INIT_MX35 ; init section for the CPU CORE0_FLASH0 = FLASH_CARD ; flash section parameters CORE0_ENDIAN = LITTLE ; core is little endian CORE0_WORKSPACE = 0x10000000, 0x10000 ; workspace for flash programmer CORE0_STARTUP_MODE = RESET CORE0_USE_FAST_DOWNLOAD = YES CORE0_PATH = "tftp://192.168.5.1" ; default path [INIT_MX35] ; AIPS setup memory write32 0x43f00040 0x00000000 memory write32 0x43f00044 0x00000000 memory write32 0x43f00048 0x00000000 memory write32 0x43f0004C 0x00000000 memory write32 0x43f00050 0x00000000 memory write32 0x43f00000 0x77777777 memory write32 0x43f00004 0x77777777 memory write32 0x53f00040 0x00000000 memory write32 0x53f00044 0x00000000 memory write32 0x53f00048 0x00000000 memory write32 0x53f0004C 0x00000000 memory and32 0x53f00050 0x00FFFFFF memory write32 0x53f00000 0x77777777 memory write32 0x53f00004 0x77777777 ; MAX setup memory write32 0x43F04000 0x00302154 memory write32 0x43F04100 0x00302154 memory write32 0x43F04200 0x00302154 memory write32 0x43F04300 0x00302154 memory write32 0x43F04400 0x00302154 memory write32 0x43F04010 0x00000010 memory write32 0x43F04110 0x00000010 memory write32 0x43F04210 0x00000010 memory write32 0x43F04310 0x00000010 memory write32 0x43F04410 0x00000010 memory write32 0x43F04800 0x00000000 memory write32 0x43F04900 0x00000000 memory write32 0x43F04A00 0x00000000 memory write32 0x43F04B00 0x00000000 memory write32 0x43F04C00 0x00000000 memory write32 0x43F048D0 0x00000000 ; M3IF memory write32 0xB8003000 0x00000040 ; Clock setup memory write32 0x53F80028 0x7D006C67 ; CLKCTL_COSR memory write32 0x53F80000 0x003F4208 ; CLKCTL_CCMR memory write32 0x53F8001C 0x800B2C01 ; CLKCTL_MPCTL memory write32 0x53F80020 0x00031801 ; CLKCTL_PPCTL ;memory write32 0x53F80004 0x00821000 ; first need to set IPU_HND_BYP ;memory write32 0x53F80004 0x00821000 ; arm clock is 399Mhz and ahb clock is 133Mhz. memory write32 0x53F80004 0x00001000 ; CLKCTL_PDR0 memory write32 0x53F8002C 0xFFFFFFFF ; CLKCTL_CGR0 memory write32 0x53F80030 0xFFFFFFFF ; CLKCTL_CGR1 clock normal mem read 0x10000000 [FLASH_CARD] CHIP = CARD CPU = iMX35 FILE = ftp://192.168.10.1/tito/xldr.nb0, bin, 2 [SERIAL] ; serial port configuration BAUD = 115200 STOP_BITS = 1 PARITY = NONE ;TCP_PORT = 2001 TCP_PORT = 0 [TELNET] PROMPT = "mx35> " ; telnet prompt ;BACKSPACE = 127 ; comment out for autodetect [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 25 ; zummer volume [ACTIONS] ; user defined scripts 1 = prog_xldr 2 = prog_eboot 3 = prog_nk 4 = prog_all [prog_xldr] flash prog ftp://192.168.10.1/xldr.nb0 bin 2 [prog_eboot] flash prog ftp://192.168.10.1/EBOOT.nb0 bin 256 [prog_nk] flash prog ftp://192.168.10.1/NK.nb0 bin 768 [prog_all] run #1 run #2 run #3