;-------------------------------------------------------------------------- ; ; ; PEEDI sample target configuration file ; ; Ronetix ; ; Supported devices : Freescale iMX31, ARM1136 ; Board : Bluetechnix CM-i.MX31 ; MCIMX31LITEKIT ; ; Revision : 1.1 ; ; Date : Apr 20, 2015 ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. These licenses must be filled before using this file. ; The [LICENSE] section may contain license keys for one or more PEEDIs. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2010, 1111-1111-1111-1 ; KEY = XXXXX, 2222-2222-2222-2 ; ; The [LICENSE] section may point to an external file which contains ; license keys for one or more PEEDIs. The external file must include ; the text [LICENSE] followed by all keys. ; ; Example: ; [LICENSE] ; FILE = tftp://192.168.3.1/license.txt ; or ; FILE=eep:license.txt ; or ; FILE = ftp://user:password@192.168.3.1/license.txt ; ; ; PEEDI is shipped with license keys stored in "eep:license.txt" and ; printed on a label on the bottom side of PEEDI. ; [LICENSE] FILE=eep:license.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote ; gdb remote REMOTE_PORT = 2000 ; TCP/IP port [TARGET] PLATFORM = ARM11 ; platform is ARM11 [PLATFORM_ARM11] JTAG_CHAIN = 5,4,5,4 ; list of IR lenght of all TAP controllers in JTAG chain JTAG_CLOCK = 10, 10000 ; JTAG Clock in [kHz] - 10kHz jtag clock for init operations and 10MHz for normal work JTAG_TDO_DELAY = AUTO TRST_TYPE = OPENDRAIN ; type of TRST output: OPENDRAIN or PUSHPULL RESET_TIME = 200 ; lenght of RESET pulse in ms; 0 means no RESET CORE0 = ARM1136, 2 ; TAP is ARM7TDMI CPU CORE0_BREAKMODE = soft ; breakpoint mode CORE0_INIT = INIT_MX31 ; init section for the CPU CORE0_FLASH0 = FLASH_NOR ; NOR flash section parameters CORE0_FLASH1 = FLASH_NAND_BOOT ; NAND flash section parameters CORE0_FLASH2 = FLASH_NAND_KERNEL ; NAND flash section parameters CORE0_FLASH3 = FLASH_NAND_ROOTFS ; NAND flash section parameters CORE0_ENDIAN = LITTLE ; core is little endian CORE0_WORKSPACE_ADDR = 0x80000000 ; start address of workspace for flash programmer CORE0_WORKSPACE_LEN = 0x10000 ; length of workspace in bytes CORE0_STARTUP_MODE = RESET ;CORE0_VECTOR_CATCH_MASK = 0xFF ; Default path to be used if only a file name (without the full path) is ; provided to a PEEDI command or for the FILE parameter in the Flash sections ; Examples: ; In a console: ; "flash prog tftp://192.168.3.1/image.elf" ; is equal to ; "flash prog image.elf" ; ; In a Flash Profile: ; FILE="tftp://192.168.3.1/image.bin", BIN, 0 ; is equal to ; FILE="image.bin", BIN, 0 ; CORE0_PATH = "tftp://192.168.3.1" ;CORE0_PATH = "card://" CORE0_FILE = "arm11.bin", 0xA0000000 ; Caution: ; On some boards pin.1 and pin.2 of the JTAG connector ; privide different voltages. In a such case please disconnect pin.2 ; This is necessary because on the PEEDI's side pin.1 and pin.2 are ; conencted together. ; [INIT_MX31] ; Enable Display Interface in IPU mem write 0x53FC0000 0x040 ; CCM clock control module setup ; FPM-disable, PLL reference clock = CKIH, MCU PLL enabled, MCUPLL MCU clock domain source ; clock setup 399MHz - 26MHz input, PD=1,MFI=7, MFN=27, MFD=40 mem write 0x53F80000 0x074B0B7D mem write 0x53F80004 0xFF871D50 mem write 0x53F80010 0x00271C1B ; Configure 16 bit PSRAM on CS5 mem write 0xb8002050 0x0000DCF6 mem write 0xb8002054 0X444A4541 mem write 0xb8002058 0X44443302 mem write 0xb6000000 0XCAFECAFE ; Start 16 bit NorFlash Initialization on CS0 mem write 0xb8002000 0x0000CC03 mem write 0xb8002004 0xa0330D01 mem write 0xb8002008 0x00220800 ; Configure CPLD on CS4 mem write 0xb8002040 0x0000DCF6 mem write 0xb8002044 0x444A4541 mem write 0xb8002048 0x44443302 ; SDRAM initialization ; -------------------- mem write 0xB8001010 0x00000004 ; configure the ESDRAM configuration register ESDCFG0. mem write 0xB8001004 0x006AC73A ; load ESDRAM control register 0 ESDCTL0 mem write 0xB8001000 0x92100000 mem write 0x80000f00 0x12344321 ; load ESDRAM control register 0 ESDCTL0 mem write 0xB8001000 0xa2100000 mem write 0x80000000 0x12344321 mem write 0x80000000 0x12344321 ; load ESDRAM control register 0 ESDCTL0 mem write 0xB8001000 0xb2100000 mem write8 0x80000033 0xDA mem write8 0x81000000 0xFF ; load ESDRAM control register 0 ESDCTL0 mem write 0xB8001000 0x82126080 mem write 0x80000000 0xDEADBEEF ; Rest Delay Line Measurement for DDR mem write 0xB8001010 0x0000000C mem read 0x80000000 [FLASH_NOR] CHIP = CFI_FLASH ; flash chip ACCESS_METHOD = AGENT ; program method CHECK_ID = YES ; check chip ID CHIP_WIDTH = 16 ; chip is in 16 bit configuration CHIP_COUNT = 1 ; one chip is used BASE_ADDR = 0xA0000000 ; chip is mapped at 0x1000000 FILE = "arm11.bin", 0xA0000000 AUTO_ERASE = NO ; erase before program AUTO_LOCK = NO ; lock after program [FLASH_NAND_BOOT] CHIP = NAND_FLASH CPU = iMX31 FILE = "bootloader.bin", 0x0000000 ERASE_BAD_BLOCKS = NO OOB_INFO = IMX_ECC [FLASH_NAND_KERNEL] CHIP = NAND_FLASH CPU = iMX31 FILE = "kernel.bin", BIN, 0x20000 ERASE_BAD_BLOCKS = NO OOB_INFO = IMX_ECC [FLASH_NAND_ROOTFS] CHIP = NAND_FLASH CPU = iMX31 FILE = "rootfs.jffs2", BIN, 0x420000 ERASE_BAD_BLOCKS = NO OOB_INFO = IMX_ECC [SERIAL] ; serial port configuration BAUD = 115200 STOP_BITS = 1 PARITY = NONE TCP_PORT = 0 [TELNET] PROMPT = "mx31> " ; telnet prompt ;BACKSPACE = 127 ; comment out for autodetect [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 25 ; zummer volume [ACTIONS] ; user defined scripts 1 = erase 2 = prog [erase] ; erase flash flash erase [prog] ; program flash flash program