diff -Naur PM9263_old/SRC/DRIVERS/Emacb/dp83848.c PM9263/SRC/DRIVERS/Emacb/dp83848.c --- PM9263_old/SRC/DRIVERS/Emacb/dp83848.c 1970-01-01 01:00:00.000000000 +0100 +++ PM9263/SRC/DRIVERS/Emacb/dp83848.c 2008-08-15 14:57:38.000000000 +0200 @@ -0,0 +1,428 @@ +/* + * National Semiconductor DP83848 PHY Driver for SAM9263 + * (TMS320DM644x) based boards. + * + * Copyright (C) Sergey Kubushyn <ksi at koi8.net>, 2007. + * + * -------------------------------------------------------- + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include "phyInterface.h" + + +/* National Semiconductor PHYSICAL LAYER TRANSCEIVER DP83848 */ + +#define DP83848_CTL_REG 0x0 /* Basic Mode Control Reg */ +#define DP83848_STAT_REG 0x1 /* Basic Mode Status Reg */ +#define DP83848_PHYID1_REG 0x2 /* PHY Idendifier Reg 1 */ +#define DP83848_PHYID2_REG 0x3 /* PHY Idendifier Reg 2 */ +#define DP83848_ANA_REG 0x4 /* Auto_Neg Advt Reg */ +#define DP83848_ANLPA_REG 0x5 /* Auto_neg Link Partner Ability Reg */ +#define DP83848_ANE_REG 0x6 /* Auto-neg Expansion Reg */ +#define DP83848_PHY_STAT_REG 0x10 /* PHY Status Register */ +#define DP83848_PHY_INTR_CTRL_REG 0x11 /* PHY Interrupt Control Register */ +#define DP83848_PHY_RBR_REG 0x17 /* PHY RMII and Bypass Register */ +#define DP83848_PHY_CTRL_REG 0x19 /* PHY Status Register */ + +/*--Bit definitions: DP83848_CTL_REG */ +#define DP83848_RESET (1 << 15) /* 1= S/W Reset */ +#define DP83848_LOOPBACK (1 << 14) /* 1=loopback Enabled */ +#define DP83848_SPEED_SELECT (1 << 13) +#define DP83848_AUTONEG (1 << 12) +#define DP83848_POWER_DOWN (1 << 11) +#define DP83848_ISOLATE (1 << 10) +#define DP83848_RESTART_AUTONEG (1 << 9) +#define DP83848_DUPLEX_MODE (1 << 8) +#define DP83848_COLLISION_TEST (1 << 7) + +/*--Bit definitions: DP83848_STAT_REG */ +#define DP83848_100BASE_T4 (1 << 15) +#define DP83848_100BASE_TX_FD (1 << 14) +#define DP83848_100BASE_TX_HD (1 << 13) +#define DP83848_10BASE_T_FD (1 << 12) +#define DP83848_10BASE_T_HD (1 << 11) +#define DP83848_MF_PREAMB_SUPPR (1 << 6) +#define DP83848_AUTONEG_COMP (1 << 5) +#define DP83848_RMT_FAULT (1 << 4) +#define DP83848_AUTONEG_ABILITY (1 << 3) +#define DP83848_LINK_STATUS (1 << 2) +#define DP83848_JABBER_DETECT (1 << 1) +#define DP83848_EXTEND_CAPAB (1 << 0) + +/*--definitions: DP83848_PHYID1 */ +#define DP83848_PHYID1_OUI 0x2000 +#define DP83848_PHYID2_OUI 0x5c90 +#define MII_DP83848_ID ((DP83848_PHYID1_OUI << 16) | DP83848_PHYID2_OUI) + +/*--Bit definitions: DP83848_ANAR, DP83848_ANLPAR */ +#define DP83848_NP (1 << 15) +#define DP83848_ACK (1 << 14) +#define DP83848_RF (1 << 13) +#define DP83848_PAUSE (1 << 10) +#define DP83848_T4 (1 << 9) +#define DP83848_TX_FDX (1 << 8) +#define DP83848_TX_HDX (1 << 7) +#define DP83848_10_FDX (1 << 6) +#define DP83848_10_HDX (1 << 5) +#define DP83848_AN_IEEE_802_3 0x0001 + +/*--Bit definitions: DP83848_ANER */ +#define DP83848_PDF (1 << 4) +#define DP83848_LP_NP_ABLE (1 << 3) +#define DP83848_NP_ABLE (1 << 2) +#define DP83848_PAGE_RX (1 << 1) +#define DP83848_LP_AN_ABLE (1 << 0) + +/*--Bit definitions: DP83848_PHY_STAT */ +#define DP83848_RX_ERR_LATCH (1 << 13) +#define DP83848_POLARITY_STAT (1 << 12) +#define DP83848_FALSE_CAR_SENSE (1 << 11) +#define DP83848_SIG_DETECT (1 << 10) +#define DP83848_DESCRAM_LOCK (1 << 9) +#define DP83848_PAGE_RCV (1 << 8) +#define DP83848_PHY_RMT_FAULT (1 << 6) +#define DP83848_JABBER (1 << 5) +#define DP83848_AUTONEG_COMPLETE (1 << 4) +#define DP83848_LOOPBACK_STAT (1 << 3) +#define DP83848_DUPLEX (1 << 2) +#define DP83848_SPEED (1 << 1) +#define DP83848_LINK (1 << 0) + +/*--Bit definitions: DP83848_PHY_RBR_REG */ +#define DP83848_RMII_MODE (1 << 5) + + + +static BOOL PHY_Reset(T_MAC_INFO *pMacInfo,unsigned char ucPhyAddr) +{ +#if 0 + RETAILMSG(1,(TEXT("RESET PHY!!!\r\n"))); + pMacInfo->write_phy(pMacInfo->pDeviceLocation,ucPhyAddr,DP83848_CTL_REG,DP83848_RESET); +#endif +#if 1 +//static uchar dp83848_init_phy (AT91PS_EMAC p_mac) { +//uchar ret = TRUE; +// at91_EmacEnableMDIO (p_mac); +// if (!dp83848_get_link_speed(p_mac)) { +// /* Try another time */ +// udelay(100000); +// ret = dp83848_get_link_speed(p_mac); +// } +// +// /* Disable PHY Interrupts */ +// if (!at91_EmacWritePhy (p_mac, PhyAddress, DP83848_PHY_INTR_CTRL_REG, 0)) +// return FALSE; +// +// at91_EmacDisableMDIO (p_mac); +// return(ret); + //RETAILMSG(1,(TEXT("RESET INTERRUPT PHY!!!\r\n"))); + pMacInfo->write_phy(pMacInfo->pDeviceLocation,ucPhyAddr,DP83848_PHY_INTR_CTRL_REG,0x0001); +#endif + return TRUE; +} + + +static BOOL PHY_StartAutoNegociation(T_MAC_INFO *pMacInfo,unsigned char ucPhyAddr) +{ + pMacInfo->write_phy(pMacInfo->pDeviceLocation,ucPhyAddr,DP83848_CTL_REG,DP83848_AUTONEG | DP83848_RESTART_AUTONEG); + return TRUE; +} + + +static BOOL PHY_WaitForLink(T_MAC_INFO *pMacInfo,unsigned char ucPhyAddr, DWORD dwTimeout) +{ + DWORD dwValue; + DWORD dwEndOfWait = OALGetTickCount() + dwTimeout; + do + { + /* Link status is latched, so read twice to get current value */ + pMacInfo->read_phy(pMacInfo->pDeviceLocation,ucPhyAddr,DP83848_STAT_REG,&dwValue); + pMacInfo->read_phy(pMacInfo->pDeviceLocation,ucPhyAddr,DP83848_STAT_REG,&dwValue); +#ifdef DBG_PHY + RETAILMSG(1,(TEXT("Status = %d\r\n"),dwValue)); +#endif + if (dwValue & DP83848_LINK_STATUS) + { + break; + } + } + while (OALGetTickCount() < dwEndOfWait); + + if ((dwValue & DP83848_LINK_STATUS)==0) + { + return FALSE; + } + + return TRUE; +} + +static BOOL PHY_WaitForAutonegociationComplete(T_MAC_INFO *pMacInfo,unsigned char ucPhyAddr, DWORD dwTimeout) +{ + DWORD dwValue; + DWORD dwEndOfWait = OALGetTickCount() + dwTimeout; + do + { + /* Link status is latched, so read twice to get current value */ + pMacInfo->read_phy(pMacInfo->pDeviceLocation,ucPhyAddr,DP83848_STAT_REG,&dwValue); + pMacInfo->read_phy(pMacInfo->pDeviceLocation,ucPhyAddr,DP83848_STAT_REG,&dwValue); + if (dwValue & DP83848_AUTONEG_COMP) + { + break; + } + } + while (OALGetTickCount() < dwEndOfWait); + + if ((dwValue & DP83848_AUTONEG_COMP)==0) + { + return FALSE; + } + + return TRUE; +} + + +static BOOL PHY_GetID(T_MAC_INFO *pMacInfo,unsigned char ucPhyAddr,DWORD* pdwID) +{ + DWORD dwID,dwValue; + pMacInfo->read_phy(pMacInfo->pDeviceLocation,ucPhyAddr,DP83848_PHYID1_REG,&dwValue); + dwID = dwValue << 16; + +#ifdef DBG_PHY_0 + RETAILMSG(1,(TEXT("PHY ID1: 0x%x\r\n"),dwValue)); +#endif + + dwValue = 0; + pMacInfo->read_phy(pMacInfo->pDeviceLocation,ucPhyAddr,DP83848_PHYID2_REG,&dwValue); + dwID |= dwValue; + +#ifdef DBG_PHY_0 + RETAILMSG(1,(TEXT("PHY ID2: 0x%x\r\n"),dwValue)); +#endif + + + if (pdwID) + { + *pdwID = dwID; + return TRUE; + } + else + { + return FALSE; + } +} + +static BOOL PHY_CheckID(T_MAC_INFO *pMacInfo,unsigned char ucPhyAddr) +{ +#define ID_MASK 0xFFFFF800 + DWORD dwID,dwID2; + int i =0; + PHY_GetID(pMacInfo,ucPhyAddr,&dwID); + PHY_GetID(pMacInfo,ucPhyAddr,&dwID2); + + for(i=0;i<200 && dwID==dwID2;i++) + PHY_GetID(pMacInfo,ucPhyAddr,&dwID); + +#ifdef DBG_PHY + if(dwID!=dwID2) + RETAILMSG(1,(TEXT("PHY ID instable 1: %d, 2: %d.\r\n"),dwID,dwID2)); + else + RETAILMSG(1,(TEXT("PHY ID : 0x%x"),dwID)); +#endif + PHY_GetID(pMacInfo,ucPhyAddr,&dwID); + if ((dwID & ID_MASK) != (MII_DP83848_ID & ID_MASK)) + { + return FALSE; + } + else + { + return TRUE; + } +} + + +static BOOL PHY_SetConfiguration(T_MAC_INFO *pMacInfo,unsigned char ucPhyAddr, T_PHY_CONFIGURATION* pPhyCfg) +{ + DWORD dwControlReg; + DWORD dwDavicomSpecifiedConfReg; + // Check parameters ! + if (pPhyCfg == NULL) + { + return FALSE; + } + + pMacInfo->read_phy(pMacInfo->pDeviceLocation,ucPhyAddr,DP83848_PHY_RBR_REG,&dwDavicomSpecifiedConfReg); + + if ((pPhyCfg->bRMII == FALSE) && (dwDavicomSpecifiedConfReg & DP83848_RMII_MODE)) + { + RETAILMSG(1,(TEXT("PHY_SetConfiguration : MII mode not available\r\n"))); + return FALSE; + } + if ((pPhyCfg->bRMII == TRUE) && (!(dwDavicomSpecifiedConfReg & DP83848_RMII_MODE))) + { + RETAILMSG(1,(TEXT("PHY_SetConfiguration : RMII mode not available\r\n"))); + return FALSE; + } + + + + if (pPhyCfg->bAutoNegociation) + { + return PHY_StartAutoNegociation(pMacInfo,ucPhyAddr); + } + + + // Check parameters + if ((pPhyCfg->dwSpeed != SPEED_100) && (pPhyCfg->dwSpeed != SPEED_10)) + { + return FALSE; + } + + + dwControlReg = 0; + if (pPhyCfg->dwSpeed == SPEED_100) + { + dwControlReg |= DP83848_SPEED_SELECT; + } + if (pPhyCfg->bFullDuplex) + { + dwControlReg |= DP83848_DUPLEX_MODE; + } + + + pMacInfo->write_phy(pMacInfo->pDeviceLocation,ucPhyAddr,DP83848_CTL_REG,dwControlReg); + + return FALSE; +} + + + +static BOOL PHY_GetConfiguration(T_MAC_INFO *pMacInfo,unsigned char ucPhyAddr, T_PHY_CONFIGURATION* pPhyCfg) +{ + DWORD dwCtrlReg; + DWORD dwStatusReg; + DWORD dwLinkPartnerReg; + DWORD dwDavicomSpecifiedConfReg; + + if (pPhyCfg == NULL) + { + return FALSE; + } + + + pMacInfo->read_phy(pMacInfo->pDeviceLocation,ucPhyAddr,DP83848_CTL_REG,&dwCtrlReg); + pMacInfo->read_phy(pMacInfo->pDeviceLocation,ucPhyAddr,DP83848_STAT_REG,&dwStatusReg); + + RETAILMSG(1,(TEXT("CONTROL REG : 0x%x\r\n"), dwCtrlReg)); + RETAILMSG(1,(TEXT("STATUS REG : 0x%x\r\n"), dwStatusReg)); + + if (dwCtrlReg & DP83848_AUTONEG) + { + pPhyCfg->bAutoNegociation = TRUE; + + /* AutoNegotiation is enabled */ + if (!(dwStatusReg & DP83848_AUTONEG_COMP)) + { + return FALSE; /* auto-negotitation in progress */ + } + + + pMacInfo->read_phy(pMacInfo->pDeviceLocation,ucPhyAddr,DP83848_ANLPA_REG,&dwLinkPartnerReg); + if ((dwLinkPartnerReg & DP83848_TX_FDX) || (dwLinkPartnerReg & DP83848_TX_HDX)) + { + pPhyCfg->dwSpeed = SPEED_100; + } + else + { + pPhyCfg->dwSpeed = SPEED_10; + } + + if ((dwLinkPartnerReg & DP83848_TX_FDX) || (dwLinkPartnerReg & DP83848_10_FDX)) + { + pPhyCfg->bFullDuplex = TRUE; + } + else + { + pPhyCfg->bFullDuplex = FALSE; + } + } + else + { + pPhyCfg->bAutoNegociation = FALSE; + if (dwCtrlReg & DP83848_SPEED_SELECT) + { + pPhyCfg->dwSpeed = SPEED_100; + } + else + { + pPhyCfg->dwSpeed = SPEED_10; + } + if (dwCtrlReg & DP83848_DUPLEX_MODE) + { + pPhyCfg->bFullDuplex = TRUE; + } + else + { + pPhyCfg->bFullDuplex = FALSE; + } + } + + pMacInfo->read_phy(pMacInfo->pDeviceLocation,ucPhyAddr,DP83848_PHY_RBR_REG,&dwDavicomSpecifiedConfReg); + + if (dwDavicomSpecifiedConfReg & DP83848_RMII_MODE) + { + pPhyCfg->bRMII = TRUE; + } + else + { + pPhyCfg->bRMII = FALSE; + } + + return TRUE; +} + + +static const WCHAR PhyName[] = L"DP83848"; + + + +T_PHY_INTERFACE DP83848_PhyInterface = { + PHY_Reset, + PHY_SetConfiguration, + PHY_GetConfiguration, + PHY_StartAutoNegociation, + PHY_WaitForLink, + PHY_WaitForAutonegociationComplete, + PHY_GetID, + PHY_CheckID, + PhyName +}; + + + + +//! @} + +//! @} +//! @} + +//! @} \ No newline at end of file diff -Naur PM9263_old/SRC/DRIVERS/Emacb/Emac.c PM9263/SRC/DRIVERS/Emacb/Emac.c --- PM9263_old/SRC/DRIVERS/Emacb/Emac.c 2008-06-12 18:45:50.000000000 +0200 +++ PM9263/SRC/DRIVERS/Emacb/Emac.c 2008-08-15 14:49:28.000000000 +0200 @@ -36,6 +36,8 @@ #define UNDERRUN 1 #define ETHERNET_BUFFER_BASE_PHYSICAL 0x20059000 + + extern void OEMWriteDebugString(WCHAR*); #define INC_MODULO(x,y) (x) < (y-1) ? (x+1) : 0 @@ -581,7 +583,8 @@ -extern T_PHY_INTERFACE DM9161A_PhyInterface; +// rm extern T_PHY_INTERFACE DM9161A_PhyInterface; +extern T_PHY_INTERFACE DP83848_PhyInterface; //*---------------------------------------------------------------------------- //* \fn AT91F_EMACInit @@ -600,7 +603,8 @@ UCHAR ucPhyAddr; T_PHY_INTERFACE *PhyList[] = { - &DM9161A_PhyInterface, + // rm &DM9161A_PhyInterface, + &DP83848_PhyInterface, }; //AT91PS_MATRIX pMatrix = (AT91PS_MATRIX) OALPAtoVA((DWORD)AT91C_BASE_MATRIX, FALSE); @@ -662,7 +666,11 @@ } RETAILMSG(1,(TEXT("Found Phy (%s) at address %d\r\n"),pPhyInterface->wzName,ucPhyAddr)); - //pPhyInterface->PHY_Reset(&macInfo,ucPhyAddr); +#if 1 + // rm disabilita interrupt phy e pin in out + pPhyInterface->PHY_Reset(&macInfo,ucPhyAddr); +#endif + #define GET_LINK_SPEED_TIMEOUT 10000 #ifdef IS_MISTRAL diff -Naur PM9263_old/SRC/DRIVERS/Emacb/PhyInterface.h PM9263/SRC/DRIVERS/Emacb/PhyInterface.h --- PM9263_old/SRC/DRIVERS/Emacb/PhyInterface.h 2007-04-13 15:35:48.000000000 +0200 +++ PM9263/SRC/DRIVERS/Emacb/PhyInterface.h 2008-08-15 14:48:42.000000000 +0200 @@ -25,6 +25,8 @@ #define SPEED_100 100 #define SPEED_10 10 +#undef DBG_PHY + /// MAC information structure needed by the PHY typedef struct { void (*read_phy)(PVOID pDeviceLocation, unsigned char phy_addr, unsigned char address, DWORD *dwValue); //!< \brief function to read a PHY register diff -Naur PM9263_old/SRC/DRIVERS/Emacb/sources PM9263/SRC/DRIVERS/Emacb/sources --- PM9263_old/SRC/DRIVERS/Emacb/sources 2007-04-03 18:57:56.000000000 +0200 +++ PM9263/SRC/DRIVERS/Emacb/sources 2008-11-20 19:53:20.000000000 +0100 @@ -11,6 +11,6 @@ NOMIPS16CODE=1 SOURCES= \ Emac.c \ - dm9161A.c \ + dp83848.c \ diff -Naur PM9263_old/SRC/DRIVERS/NandFlash/NandFlash.c PM9263/SRC/DRIVERS/NandFlash/NandFlash.c --- PM9263_old/SRC/DRIVERS/NandFlash/NandFlash.c 2008-02-25 17:36:48.000000000 +0100 +++ PM9263/SRC/DRIVERS/NandFlash/NandFlash.c 2008-08-14 21:00:26.000000000 +0200 @@ -39,7 +39,8 @@ #include "atmel_nandflash.h" #define A91C_NAND_ENABLE_PIN AT91C_PIN_PD(15) -#define A91C_NAND_READY_PIN AT91C_PIN_PA(22) +//#define A91C_NAND_READY_PIN AT91C_PIN_PA(22) +#define A91C_NAND_READY_PIN AT91C_PIN_PB(30) #define A91C_NAND_ALE (1<<21) #define A91C_NAND_CLE (1<<22) diff -Naur PM9263_old/SRC/DRIVERS/SDHC/at91sam9263ek_slot.cpp PM9263/SRC/DRIVERS/SDHC/at91sam9263ek_slot.cpp --- PM9263_old/SRC/DRIVERS/SDHC/at91sam9263ek_slot.cpp 2008-01-22 12:03:00.000000000 +0100 +++ PM9263/SRC/DRIVERS/SDHC/at91sam9263ek_slot.cpp 2008-08-20 01:37:10.000000000 +0200 @@ -15,7 +15,16 @@ #include #include "atmel_gpio.h" +#define RONETIX +#undef ATMEL +#undef SM + +#define DBG_SD + +#ifdef ATMEL #define USE_GPIO16_FOR_VOLTAGE_SELECTION +#endif + //#define CARDETECTSIMULATION extern "C" int pio_setup (const struct pio_desc *pio_desc, int nb_pio); @@ -69,8 +78,10 @@ BOOL CSDHCSlotAT91::IsPresent() { - //DEBUGMSG(SDCARD_ZONE_INFO, (_T("CSDHCSlotAT91 : -->IsPresent\n\r"))); - //DEBUGMSG(SDCARD_ZONE_INFO, (_T("CSDHCSlotAT91 : <--IsPresent\n\r"))); +#ifdef DBG_SD + DEBUGMSG(SDCARD_ZONE_INFO, (_T("CSDHCSlotAT91 : -->IsPresent\n\r"))); + DEBUGMSG(SDCARD_ZONE_INFO, (_T("CSDHCSlotAT91 : <--IsPresent\n\r"))); +#endif return m_bAT91CardPresent; } @@ -82,6 +93,7 @@ { goto exit; } +#ifdef ATMEL if ((m_dwControllerIndex == 0) && (dwSlot == 0)) { static const struct pio_desc hw_pioSlot0_0[] = @@ -114,8 +126,78 @@ bResult = FALSE; goto exit; } +#endif +#ifdef RONETIX + if ((m_dwControllerIndex == 0) && (dwSlot == 0)) + { + static const struct pio_desc hw_pioSlot0_0[] = + { + {"DETECT", AT91C_PIN_PA(21), 0, PIO_PULLUP, PIO_INPUT}, + {"WP", AT91C_PIN_PA(16), 0, PIO_PULLUP, PIO_INPUT}, + }; + pio_setup(hw_pioSlot0_0,sizeof(hw_pioSlot0_0)/sizeof(hw_pioSlot0_0[0])); + m_dwDetectPin = AT91C_PIN_PA(21); + m_dwWriteProtectPin = AT91C_PIN_PA(16); + m_dwSlotID = SLOT_A; + } + else if ((m_dwControllerIndex == 1) && (dwSlot == 0)) + { + static const struct pio_desc hw_pioSlot1_0[] = + { + {"DETECT", AT91C_PIN_PA(21), 0, PIO_PULLUP, PIO_INPUT}, + {"WP", AT91C_PIN_PA(16), 0, PIO_PULLUP, PIO_INPUT}, + }; + pio_setup(hw_pioSlot1_0,sizeof(hw_pioSlot1_0)/sizeof(hw_pioSlot1_0[0])); + m_dwDetectPin = AT91C_PIN_PA(21); + m_dwWriteProtectPin = AT91C_PIN_PA(16); + m_dwSlotID = SLOT_A; + } + else + { + m_dwWriteProtectPin = 0xFFFFFFFF; + m_dwDetectPin = 0xFFFFFFFF; + DEBUGCHK(0); + bResult = FALSE; + goto exit; + } +#endif +#ifdef SM + if ((m_dwControllerIndex == 0) && (dwSlot == 0)) + { + static const struct pio_desc hw_pioSlot0_0[] = + { + {"DETECT", AT91C_PIN_PE(22), 0, PIO_PULLUP, PIO_INPUT}, + {"WP", AT91C_PIN_PE(22), 0, PIO_PULLUP, PIO_INPUT}, + }; + + + pio_setup(hw_pioSlot0_0,sizeof(hw_pioSlot0_0)/sizeof(hw_pioSlot0_0[0])); + m_dwDetectPin = AT91C_PIN_PE(22); + m_dwWriteProtectPin = AT91C_PIN_PE(22); + m_dwSlotID = SLOT_A; + } + else if ((m_dwControllerIndex == 1) && (dwSlot == 0)) + { + static const struct pio_desc hw_pioSlot1_0[] = + { + {"DETECT", AT91C_PIN_PA(21), 0, PIO_PULLUP, PIO_INPUT}, + {"WP", AT91C_PIN_PA(21), 0, PIO_PULLUP, PIO_INPUT}, + }; + pio_setup(hw_pioSlot1_0,sizeof(hw_pioSlot1_0)/sizeof(hw_pioSlot1_0[0])); + m_dwDetectPin = AT91C_PIN_PA(21); + m_dwWriteProtectPin = AT91C_PIN_PA(21); + m_dwSlotID = SLOT_B; + } + else + { + m_dwWriteProtectPin = 0xFFFFFFFF; + m_dwDetectPin = 0xFFFFFFFF; + DEBUGCHK(0); + bResult = FALSE; + goto exit; + } +#endif - exit: return bResult; } diff -Naur PM9263_old/SRC/DRIVERS/SDMEMORY/driver/sdmemory.c PM9263/SRC/DRIVERS/SDMEMORY/driver/sdmemory.c --- PM9263_old/SRC/DRIVERS/SDMEMORY/driver/sdmemory.c 2008-06-02 19:25:46.000000000 +0200 +++ PM9263/SRC/DRIVERS/SDMEMORY/driver/sdmemory.c 2008-08-20 00:49:28.000000000 +0200 @@ -37,6 +37,10 @@ static HANDLE g_hSemaphore; +#define RONETIX 1 +#undef ATMEL +#undef SM + //----------------------------------------------------------------------------- //! \fn BOOL SDMemoryBoardSpecificInit(DWORD dwSlotNumber) //! @@ -225,7 +229,7 @@ BOOL SDMemoryBoardSpecificPIOConfiguration(DWORD dwSlotNumber) { BOOL bResult = TRUE; - +#ifdef ATMEL static const struct pio_desc hw_pioSLOT0[] = { {"MCI1DA0", AT91C_PIN_PA(8), 0, PIO_PULLUP, PIO_PERIPH_A}, @@ -244,8 +248,51 @@ {"MCI0DB2", AT91C_PIN_PA(4), 0, PIO_PULLUP, PIO_PERIPH_A}, {"MCI0DB1", AT91C_PIN_PA(3), 0, PIO_PULLUP, PIO_PERIPH_A}, {"MCI0CK", AT91C_PIN_PA(12), 0, PIO_PULLUP, PIO_PERIPH_A}, - {"PE20", AT91C_PIN_PE(20), 0, PIO_PULLUP, PIO_OUTPUT}, + {"PE20 ", AT91C_PIN_PE(20), 0, PIO_PULLUP, PIO_OUTPUT}, + }; +#endif +#ifdef RONETIX + static const struct pio_desc hw_pioSLOT0[] = + { + {"MCI1DA0", AT91C_PIN_PA(8), 0, PIO_PULLUP, PIO_PERIPH_A}, + {"MCI1CDA", AT91C_PIN_PA(7), 0, PIO_DEFAULT, PIO_PERIPH_A}, + {"MCI1CK", AT91C_PIN_PA(6), 0, PIO_PULLUP, PIO_PERIPH_A}, + {"MCI1DA1", AT91C_PIN_PA(9), 0, PIO_PULLUP, PIO_PERIPH_A}, + {"MCI1DA2", AT91C_PIN_PA(10), 0, PIO_PULLUP, PIO_PERIPH_A}, + {"MCI1DA3", AT91C_PIN_PA(11), 0, PIO_PULLUP, PIO_PERIPH_A}, + }; +// connettore dual foot + static const struct pio_desc hw_pioSLOT1[] = + { + {"MCI1DA0", AT91C_PIN_PA(8), 0, PIO_PULLUP, PIO_PERIPH_A}, + {"MCI1CDA", AT91C_PIN_PA(7), 0, PIO_DEFAULT, PIO_PERIPH_A}, + {"MCI1CK", AT91C_PIN_PA(6), 0, PIO_PULLUP, PIO_PERIPH_A}, + {"MCI1DA1", AT91C_PIN_PA(9), 0, PIO_PULLUP, PIO_PERIPH_A}, + {"MCI1DA2", AT91C_PIN_PA(10), 0, PIO_PULLUP, PIO_PERIPH_A}, + {"MCI1DA3", AT91C_PIN_PA(11), 0, PIO_PULLUP, PIO_PERIPH_A}, + }; +#endif +#ifdef SM + static const struct pio_desc hw_pioSLOT0[] = + { + {"MCI1DA0", AT91C_PIN_PA(8), 0, PIO_PULLUP, PIO_PERIPH_A}, + {"MCI1CDA", AT91C_PIN_PA(7), 0, PIO_DEFAULT, PIO_PERIPH_A}, + {"MCI1CK", AT91C_PIN_PA(6), 0, PIO_PULLUP, PIO_PERIPH_A}, + {"MCI1DA1", AT91C_PIN_PA(9), 0, PIO_PULLUP, PIO_PERIPH_A}, + {"MCI1DA2", AT91C_PIN_PA(10), 0, PIO_PULLUP, PIO_PERIPH_A}, + {"MCI1DA3", AT91C_PIN_PA(11), 0, PIO_PULLUP, PIO_PERIPH_A}, + }; + + static const struct pio_desc hw_pioSLOT1[] = + { + {"MCI0DB0", AT91C_PIN_PA(17), 0, PIO_PULLUP, PIO_PERIPH_A}, + {"MCI0CDB", AT91C_PIN_PA(16), 0, PIO_PULLUP, PIO_PERIPH_A}, + {"MCI0DB3", AT91C_PIN_PA(20), 0, PIO_PULLUP, PIO_PERIPH_A}, + {"MCI0DB2", AT91C_PIN_PA(19), 0, PIO_PULLUP, PIO_PERIPH_A}, + {"MCI0DB1", AT91C_PIN_PA(18), 0, PIO_PULLUP, PIO_PERIPH_A}, + {"MCI0CK", AT91C_PIN_PA(12), 0, PIO_PULLUP, PIO_PERIPH_A}, }; +#endif switch (dwSlotNumber) { @@ -284,14 +331,32 @@ BOOL SDMemoryBoardSpecificIsWriteProtected(DWORD dwSlotNumber) { BOOL bWriteProtected; +#ifdef ATMEL static const struct pio_desc hw_pioSLOT0 = {"WriteProtected", AT91C_PIN_PE(19), 0, PIO_DEFAULT, PIO_INPUT}; static const struct pio_desc hw_pioSLOT1 = {"WriteProtected", AT91C_PIN_PE(17), 0, PIO_DEFAULT, PIO_INPUT}; - +#endif +#ifdef RONETIX + static const struct pio_desc hw_pioSLOT0 = {"WriteProtected", AT91C_PIN_PA(16), 0, PIO_DEFAULT, PIO_INPUT}; + static const struct pio_desc hw_pioSLOT1 = {"WriteProtected", AT91C_PIN_PA(16), 0, PIO_DEFAULT, PIO_INPUT}; +#endif +#ifdef SM + //nessuno controllo + //static const struct pio_desc hw_pioSLOT0 = {"WriteProtected", AT91C_PIN_PE(22), 0, PIO_DEFAULT, PIO_INPUT}; + //static const struct pio_desc hw_pioSLOT1 = {"WriteProtected", AT91C_PIN_PA(21), 0, PIO_DEFAULT, PIO_INPUT}; +#endif switch (dwSlotNumber) { case 0: pio_setup(&hw_pioSLOT0, sizeof(hw_pioSLOT0)/sizeof(struct pio_desc)); +#ifdef ATMEL if (pio_get_value(AT91C_PIN_PE(19))) +#endif +#ifdef RONETIX + if (pio_get_value(AT91C_PIN_PA(16))) +#endif +#ifdef ATMEL + if (0) +#endif { bWriteProtected = TRUE; } @@ -302,7 +367,16 @@ break; case 1: pio_setup(&hw_pioSLOT1, sizeof(hw_pioSLOT1)/sizeof(struct pio_desc)); +#ifdef ATMEL if (pio_get_value(AT91C_PIN_PE(17))) +#endif +#ifdef RONETIX + if (pio_get_value(AT91C_PIN_PA(16))) +#endif +#ifdef SM + if (0) +#endif + { bWriteProtected = TRUE; } diff -Naur PM9263_old/SRC/DRIVERS/SDMEMORY/Loader/sdmem_loader.c PM9263/SRC/DRIVERS/SDMEMORY/Loader/sdmem_loader.c --- PM9263_old/SRC/DRIVERS/SDMEMORY/Loader/sdmem_loader.c 2007-06-07 15:00:54.000000000 +0200 +++ PM9263/SRC/DRIVERS/SDMEMORY/Loader/sdmem_loader.c 2008-08-20 01:17:34.000000000 +0200 @@ -31,6 +31,9 @@ #define MASK_SLOT_A (1<<0) #define MASK_SLOT_B (1<<1) +#define RONETIX 1 +#undef ATMEL +#undef SM // Global variables. HANDLE gSDMMCDetectThread; @@ -45,7 +48,16 @@ //----------------------------------------------------------------------------- BOOL IsInsertedOnSlotA() { +#ifdef ATMEL return (pio_get_value(AT91C_PIN_PE(18))) ? FALSE : TRUE; +#endif +#ifdef RONETIX + return (pio_get_value(AT91C_PIN_PA(21))) ? FALSE : TRUE; +#endif +#ifdef SM + return (pio_get_value(AT91C_PIN_PE(18))) ? FALSE : TRUE; +#endif + } //----------------------------------------------------------------------------- @@ -58,7 +70,15 @@ //----------------------------------------------------------------------------- BOOL IsInsertedOnSlotB() { +#ifdef ATMEL return (pio_get_value(AT91C_PIN_PE(16))) ? FALSE : TRUE; +#endif +#ifdef RONETIX + return (pio_get_value(AT91C_PIN_PA(21))) ? FALSE : TRUE; +#endif +#ifdef SM + return (pio_get_value(AT91C_PIN_PE(22))) ? FALSE : TRUE; +#endif } diff -Naur PM9263_old/SRC/DRIVERS/SPI/SPI.c PM9263/SRC/DRIVERS/SPI/SPI.c --- PM9263_old/SRC/DRIVERS/SPI/SPI.c 2008-06-11 12:39:28.000000000 +0200 +++ PM9263/SRC/DRIVERS/SPI/SPI.c 2008-08-16 18:10:02.000000000 +0200 @@ -43,12 +43,15 @@ #define SPI0_MISO AT91C_PIN_PA(0) #define SPI0_MOSI AT91C_PIN_PA(1) #define SPI0_SPCK AT91C_PIN_PA(2) -#define SPI0_NPCS3B AT91C_PIN_PB(11) +//#define SPI0_NPCS3B AT91C_PIN_PB(11) +#define SPI0_NPCS0B AT91C_PIN_PA(5) // CS Data flash, pin in peripheral mode B +#define SPI0_NPCS1B AT91C_PIN_PA(3) // CS UART // SPIO 1 #define SPI1_MISO AT91C_PIN_PB(12) #define SPI1_MOSI AT91C_PIN_PB(13) #define SPI1_SPCK AT91C_PIN_PB(14) -#define SPI1_NPCS2B AT91C_PIN_PB(17) +//#define SPI1_NPCS2B AT91C_PIN_PB(17) +#define SPI1_NPCS0A AT91C_PIN_PB(15) // CS TSC ADS7843, pin peripheral in mode A #define BUSY AT91C_PIN_PA(31) @@ -58,14 +61,15 @@ {"MISO0", SPI0_MISO , 0, PIO_PULLUP, PIO_PERIPH_B}, {"MOSI0", SPI0_MOSI , 0, PIO_PULLUP, PIO_PERIPH_B}, {"SPCK0", SPI0_SPCK , 0, PIO_PULLUP, PIO_PERIPH_B}, - {"NPCS00", SPI0_NPCS3B, 0, PIO_PULLUP, PIO_PERIPH_B}, + {"NPCS00", SPI0_NPCS0B, 0, PIO_PULLUP, PIO_PERIPH_B}, + {"NPCS10", SPI0_NPCS1B, 0, PIO_PULLUP, PIO_PERIPH_B}, }; static const struct pio_desc hw_pioSPI1[] = { {"MISO1", SPI1_MISO , 0, PIO_PULLUP, PIO_PERIPH_A}, {"MOSI1", SPI1_MOSI , 0, PIO_PULLUP, PIO_PERIPH_A}, {"SPCK1", SPI1_SPCK , 0, PIO_PULLUP, PIO_PERIPH_A}, - {"NPCS21", SPI1_NPCS2B, 0, PIO_PULLUP, PIO_PERIPH_A}, + {"NPCS01", SPI1_NPCS0A, 0, PIO_PULLUP, PIO_PERIPH_A}, }; //----------------------------------------------------------------------------- //! \fn BOOL HWSPIControllerBoardSpecificInit() @@ -292,7 +296,8 @@ int i = 0; // Chip select CS# - pio_set_value(SPI0_NPCS3B, 0); + //pio_set_value(SPI0_NPCS3B, 0); + pio_set_value(SPI1_NPCS0A, 0); // Send command for (i = 0; i <= 7; i ++) @@ -303,24 +308,29 @@ if (dwBit) { // "1" - pio_set_value(SPI0_MOSI, 1); + //pio_set_value(SPI0_MOSI, 1); + pio_set_value(SPI1_MOSI, 1); } else { // "0" - pio_set_value(SPI0_MOSI, 0); + //pio_set_value(SPI0_MOSI, 0); + pio_set_value(SPI1_MOSI, 0); } // Clock // Data acquisition on rising edge tempo(); - pio_set_value(SPI0_SPCK, 1); + //pio_set_value(SPI0_SPCK, 1); + pio_set_value(SPI1_SPCK, 1); tempo(); - pio_set_value(SPI0_SPCK, 0); + //pio_set_value(SPI0_SPCK, 0); + pio_set_value(SPI1_SPCK, 0); } // After sending the command the MOSI signal must stay to low - pio_set_value(SPI0_MOSI, 0); + //pio_set_value(SPI0_MOSI, 0); + pio_set_value(SPI1_MOSI, 0); tempo (); @@ -330,23 +340,27 @@ { //Sleep(2); tempo(); - pio_set_value(SPI0_SPCK, 1); + //pio_set_value(SPI0_SPCK, 1); + pio_set_value(SPI1_SPCK, 1); // Read data when busy done if (!(pio_get_value(BUSY))) { - (*pBufOut) = ((*pBufOut) << 1) | (pio_get_value(SPI0_MISO) ? 1 : 0); + // (*pBufOut) = ((*pBufOut) << 1) | (pio_get_value(SPI0_MISO) ? 1 : 0); + (*pBufOut) = ((*pBufOut) << 1) | (pio_get_value(SPI1_MISO) ? 1 : 0); i++; } tempo(); - pio_set_value(SPI0_SPCK, 0); + //pio_set_value(SPI0_SPCK, 0); + pio_set_value(SPI1_SPCK, 0); } tempo(); // Chip unselect - pio_set_value(SPI0_NPCS3B, 1); + //pio_set_value(SPI0_NPCS3B, 1); + pio_set_value(SPI1_NPCS0A, 1); DEBUGMSG(DEBUGSPI9263EK, (TEXT("SPIDriver: -ADS7843_Transaction Data(recu=%d) \r\n"), *pBufOut)); @@ -368,6 +382,7 @@ //----------------------------------------------------------------------------- BOOL DoSPITransactionADS7843(T_SPI_OPEN_STRUCTURE* pOpenContext,UCHAR ucCmd, WORD* pBufOut, DWORD dwLenOut) { +#if 0 const struct pio_desc hw_pio[] = { {"SPI0_MOSI", SPI0_MOSI, 1, PIO_PULLUP, PIO_OUTPUT}, {"SPI0_SPCK", SPI0_SPCK, 1, PIO_PULLUP, PIO_OUTPUT}, @@ -381,6 +396,20 @@ {"SPI0_SPCK", SPI0_SPCK, 1, PIO_PULLUP, PIO_OUTPUT}, {"SPI0_MISO", SPI0_MISO, 1, PIO_PULLUP, PIO_OUTPUT}, }; +#endif + const struct pio_desc hw_pio[] = { + {"SPI1_MOSI", SPI1_MOSI, 1, PIO_PULLUP, PIO_OUTPUT}, + {"SPI1_SPCK", SPI1_SPCK, 1, PIO_PULLUP, PIO_OUTPUT}, + {"SPI1_NPCS0A", SPI1_NPCS0A,1, PIO_PULLUP, PIO_OUTPUT}, + {"SPI1_MISO", SPI1_MISO, 1, PIO_PULLUP, PIO_INPUT}, + {"BUSY", BUSY, 1, PIO_PULLUP, PIO_INPUT}, + }; + const struct pio_desc hw_pio_all_high_state[] = { + {"SPI1_NPCS0A", SPI1_NPCS0A,1, PIO_PULLUP, PIO_OUTPUT}, + {"SPI1_MOSI", SPI1_MOSI, 1, PIO_PULLUP, PIO_OUTPUT}, + {"SPI1_SPCK", SPI1_SPCK, 1, PIO_PULLUP, PIO_OUTPUT}, + {"SPI1_MISO", SPI1_MISO, 1, PIO_PULLUP, PIO_OUTPUT}, + }; T_SPI_CONTROLLER_STRUCTURE* pSPIControllerInfo = pOpenContext->pSPIInfo->pSPIControllerInfo; @@ -396,11 +425,14 @@ pio_setup(hw_pio_all_high_state, sizeof(hw_pio_all_high_state)/sizeof(struct pio_desc)); pio_setup(hw_pio, sizeof(hw_pio)/sizeof(struct pio_desc)); - pio_set_value(SPI0_MOSI, 0); + //pio_set_value(SPI0_MOSI, 0); + pio_set_value(SPI1_MOSI, 0); tempo(); - pio_set_value(SPI0_SPCK, 0); + //pio_set_value(SPI0_SPCK, 0); + pio_set_value(SPI1_SPCK, 0); tempo(); - pio_set_value(SPI0_NPCS3B, 1); + //pio_set_value(SPI0_NPCS3B, 1); + pio_set_value(SPI1_NPCS0A, 1); tempo(); // Write Command diff -Naur PM9263_old/SRC/DRIVERS/usbhdc/at91sam9263ek_ohcd.c PM9263/SRC/DRIVERS/usbhdc/at91sam9263ek_ohcd.c --- PM9263_old/SRC/DRIVERS/usbhdc/at91sam9263ek_ohcd.c 1970-01-01 01:00:00.000000000 +0100 +++ PM9263/SRC/DRIVERS/usbhdc/at91sam9263ek_ohcd.c 2008-08-20 11:53:50.000000000 +0200 @@ -0,0 +1,93 @@ +//----------------------------------------------------------------------------- +//! \addtogroup DRIVERS +//! @{ +// +//! \addtogroup USBHost +//! @{ +//! +// All rights reserved ADENEO SAS 2006 +//! +//----------------------------------------------------------------------------- +//! \file at91sam9263ek_ohcd.c +//! +//! \brief USB Host driver for AT91SAM9263ek board +//! +//! \if cvs +//! $RCSfile: I2C.c,v $ +//! $Author: ltourlonias $ +//! $Revision: 684 $ +//! $Date: 2007-04-13 14:35:48 +0200 (ven., 13 avr. 2007) $ +//! \endif +//! +//! Description of the driver on multi lines +//----------------------------------------------------------------------------- + + +// System include +#include +#include +#include +#include + +// Local include +#include "atmel_gpio.h" +#include "AT91SAM9263_gpio.h" + +#define RONETIX +#undef ATMEL +#undef SM + +#ifdef ATMEL +#define ENA AT91C_PIN_PA(24) +#define ENB AT91C_PIN_PA(21) +#define FGLA AT91C_PIN_PA(23) +#define FGLB AT91C_PIN_PA(20) +#endif +#ifdef RONETIX +// la scheda ronetix non ha il controlloo di abilitazione ne' il power monitor +#endif +#ifdef SM +#define ENA AT91C_PIN_PB(1) +#define ENB AT91C_PIN_PB(3) +#define FGLA AT91C_PIN_PB(0) +#define FGLB AT91C_PIN_PB(2) +#endif + +//----------------------------------------------------------------------------- +//! \fn BOOL HWUSBBoardSpecificInit() +//! +//! \brief This function intialiase USB Host Power PIOs via the SP2526A-2 chip +//! +//! \return \e TRUE when all is good +//! \return \e FALSE when all is bad +//! +//! This function intialiase USB Host Power PIOs via the SP2526A-2 chip +//----------------------------------------------------------------------------- +BOOL HWUSBBoardSpecificInit() +{ + BOOL bRet = FALSE; +#ifndef RONETIX + const struct pio_desc hw_pio[] = + { + {"ENA", ENA , 0, PIO_DEFAULT, PIO_OUTPUT}, + {"ENB", ENB , 0, PIO_DEFAULT, PIO_OUTPUT}, + {"FGLA", FGLA , 0, PIO_DEFAULT, PIO_INPUT}, + {"FGLB", FGLB , 0, PIO_DEFAULT, PIO_INPUT}, + }; + bRet = pio_setup(hw_pio, sizeof(hw_pio)/sizeof(struct pio_desc)); +#else + // scheda ronetix non ha i controlli: ritorna sempre TRUE + bRet = TRUE; +#endif + + return bRet; +} + + +// End of Doxygen group USBHost +//! @} +//! @} +//----------------------------------------------------------------------------- +// End of $RCSfile: I2C.c,v $ +//----------------------------------------------------------------------------- +// diff -Naur PM9263_old/SRC/OAL/OALLIB/init.c PM9263/SRC/OAL/OALLIB/init.c --- PM9263_old/SRC/OAL/OALLIB/init.c 2008-02-05 17:30:06.000000000 +0100 +++ PM9263/SRC/OAL/OALLIB/init.c 2008-09-20 20:38:18.000000000 +0200 @@ -281,12 +281,15 @@ RETAILMSG(1,(TEXT("reset : General Reset (PowerOn)\r\n"))); pDrvGlobalArea->bForceCleanBoot = TRUE; break; + case AT91C_RSTC_RSTTYP_WAKEUP: RETAILMSG(1,(TEXT("reset : Wakeup Reset\r\n"))); pDrvGlobalArea->bForceCleanBoot = TRUE; break; case AT91C_RSTC_RSTTYP_WATCHDOG: RETAILMSG(1,(TEXT("reset : Watchdog Reset\r\n"))); + //modifca M3T per abilitazione + pDrvGlobalArea->bForceCleanBoot = TRUE; break; case AT91C_RSTC_RSTTYP_SOFTWARE: RETAILMSG(1,(TEXT("reset : warm or cold Reset\r\n")));