From 9c3308fc3cb6b7c57345bf4bd9924e8a78b3c393 Mon Sep 17 00:00:00 2001
From: Ilko Iliev <iliev@ronetix.at>
Date: Fri, 8 Mar 2019 14:22:21 +0100
Subject: [PATCH 4/4] Do not configure CPU clock if it is already done by PEEDI

Skip CPU clock setup when this is already done by PEEDI.
---
 board/at91sam9m10g45ek/at91sam9m10g45ek.c | 31 +++++++++++++----------
 driver/pmc.c                              | 22 ++++++++++++++++
 include/pmc.h                             |  1 +
 3 files changed, 40 insertions(+), 14 deletions(-)

diff --git a/board/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/at91sam9m10g45ek/at91sam9m10g45ek.c
index a57366e..447cc9b 100644
--- a/board/at91sam9m10g45ek/at91sam9m10g45ek.c
+++ b/board/at91sam9m10g45ek/at91sam9m10g45ek.c
@@ -167,20 +167,23 @@ void hw_init(void)
 	/* Disable watchdog */
 	at91_disable_wdt();
 
-	/*
-	 * At this stage the main oscillator
-	 * is supposed to be enabled PCK = MCK = MOSC
-	 */
-	pmc_init_pll(0);
-
-	/* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */
-	pmc_cfg_plla(PLLA_SETTINGS);
-
-	/* Switch PCK/MCK on Main clock output */
-	pmc_cfg_mck(BOARD_PRESCALER_MAIN_CLOCK);
-
-	/* Switch PCK/MCK on PLLA output */
-	pmc_cfg_mck(BOARD_PRESCALER_PLLA);
+	if (!pmc_init_done())
+	{
+		/*
+		 * At this stage the main oscillator
+		 * is supposed to be enabled PCK = MCK = MOSC
+		 */
+		pmc_init_pll(0);
+
+		/* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */
+		pmc_cfg_plla(PLLA_SETTINGS);
+
+		/* Switch PCK/MCK on Main clock output */
+		pmc_cfg_mck(BOARD_PRESCALER_MAIN_CLOCK);
+
+		/* Switch PCK/MCK on PLLA output */
+		pmc_cfg_mck(BOARD_PRESCALER_PLLA);
+	}
 
 	/* Enable External Reset */
 	writel(AT91C_RSTC_KEY_UNLOCK | AT91C_RSTC_URSTEN, AT91C_BASE_RSTC + RSTC_RMR);
diff --git a/driver/pmc.c b/driver/pmc.c
index 7603ce2..0672728 100644
--- a/driver/pmc.c
+++ b/driver/pmc.c
@@ -45,6 +45,24 @@ static inline unsigned int read_pmc(unsigned int offset)
 	return readl(offset + AT91C_BASE_PMC);
 }
 
+#define MCKR_SET_BY_PEEDI	0x1302
+#define PLLA_SET_BY_PEEDI	0x20C73F03
+
+/*!
+ * @brief Check if the CPU clock is already initialized by PEEDI
+ * @return true  - if already initialized
+ * @return false - if not initialized
+ */
+int pmc_init_done(void)
+{
+	unsigned long reg_mckr, reg_pllar;
+
+	reg_mckr  = read_pmc(PMC_MCKR);
+	reg_pllar = read_pmc(PMC_PLLAR);
+
+	return (reg_mckr == MCKR_SET_BY_PEEDI) && (reg_pllar == PLLA_SET_BY_PEEDI);
+}
+
 void lowlevel_clock_init()
 {
 	unsigned long tmp;
@@ -54,6 +72,10 @@ void lowlevel_clock_init()
 	 * parameters. It is assumed that ROM code set H32MXDIV, PLLADIV2,
 	 * PCK_DIV3.
 	 */
+
+	if (pmc_init_done())
+		return;
+
 	tmp = read_pmc(PMC_MCKR);
 	tmp &= (~AT91C_PMC_CSS);
 	tmp |= AT91C_PMC_CSS_SLOW_CLK;
diff --git a/include/pmc.h b/include/pmc.h
index 68a85da..7e2ca36 100644
--- a/include/pmc.h
+++ b/include/pmc.h
@@ -38,6 +38,7 @@
 #define GCK_CSS_MCK_CLK		0x04
 #define GCK_CSS_AUDIO_CLK	0x05
 
+extern int pmc_init_done(void);
 extern void pmc_init_pll(unsigned int pmc_pllicpr);
 extern int pmc_cfg_plla(unsigned int pmc_pllar);
 extern int pmc_cfg_mck(unsigned int pmc_mckr);
-- 
2.17.1